From: xingyu.wu Date: Tue, 21 Jun 2022 12:41:11 +0000 (+0800) Subject: dt-bindings:clock:Delete external clock definitions X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e39438868ee51bf2dc015f55a38fced1e08aa463;p=platform%2Fkernel%2Flinux-starfive.git dt-bindings:clock:Delete external clock definitions Move external clock definitions to C files that avoid illegal use. Signed-off-by: xingyu.wu --- diff --git a/drivers/clk/starfive/clk-starfive-jh7110-aon.c b/drivers/clk/starfive/clk-starfive-jh7110-aon.c index 737ecfe..2ea7125 100755 --- a/drivers/clk/starfive/clk-starfive-jh7110-aon.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-aon.c @@ -13,6 +13,13 @@ #include #include "clk-starfive-jh7110.h" +/* external clocks */ +#define JH7110_OSC (JH7110_CLK_END + 0) +/* aon external clocks */ +#define JH7110_GMAC0_RMII_REFIN (JH7110_CLK_END + 12) +#define JH7110_GMAC0_RGMII_RXIN (JH7110_CLK_END + 13) +#define JH7110_CLK_RTC (JH7110_CLK_END + 14) + static const struct jh7110_clk_data jh7110_clk_aon_data[] __initconst = { //source JH7110__DIV(JH7110_OSC_DIV4, "osc_div4", 4, JH7110_OSC), @@ -133,6 +140,8 @@ int __init clk_starfive_jh7110_aon_init(struct platform_device *pdev, else if ((pidx < JH7110_CLK_END) && \ (pidx > JH7110_RTC_HMS_CLK_CAL)) parents[i].hw = priv->pll[PLL_OF(pidx)]; + else if (pidx == JH7110_OSC) + parents[i].fw_name = "osc"; else if (pidx == JH7110_GMAC0_RMII_REFIN) parents[i].fw_name = "gmac0_rmii_refin"; else if (pidx == JH7110_GMAC0_RGMII_RXIN) diff --git a/drivers/clk/starfive/clk-starfive-jh7110-isp.c b/drivers/clk/starfive/clk-starfive-jh7110-isp.c index 945d0487..8fc0616 100755 --- a/drivers/clk/starfive/clk-starfive-jh7110-isp.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-isp.c @@ -24,6 +24,12 @@ #include "clk-starfive-jh7110.h" +/* external clocks */ +#define JH7110_ISP_TOP_CLK_ISPCORE_2X_CLKGEN (JH7110_CLK_ISP_END + 0) +#define JH7110_ISP_TOP_CLK_ISP_AXI_CLKGEN (JH7110_CLK_ISP_END + 1) +#define JH7110_ISP_TOP_CLK_BIST_APB_CLKGEN (JH7110_CLK_ISP_END + 2) +#define JH7110_ISP_TOP_CLK_DVP_CLKGEN (JH7110_CLK_ISP_END + 3) + static const struct jh7110_clk_data jh7110_clk_isp_data[] __initconst = { //syscon JH7110__DIV(JH7110_DOM4_APB_FUNC, "dom4_apb_func", diff --git a/drivers/clk/starfive/clk-starfive-jh7110-stg.c b/drivers/clk/starfive/clk-starfive-jh7110-stg.c index 2c151ce..2a7db38 100755 --- a/drivers/clk/starfive/clk-starfive-jh7110-stg.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-stg.c @@ -13,6 +13,11 @@ #include #include "clk-starfive-jh7110.h" +/* external clocks */ +#define JH7110_OSC (JH7110_CLK_END + 0) +/* stg external clocks */ +#define JH7110_STG_APB (JH7110_CLK_END + 11) + static const struct jh7110_clk_data jh7110_clk_stg_data[] __initconst = { //hifi4 JH7110_GATE(JH7110_HIFI4_CLK_CORE, "u0_hifi4_clk_core", @@ -145,6 +150,8 @@ int __init clk_starfive_jh7110_stg_init(struct platform_device *pdev, else if ((pidx < JH7110_CLK_STG_END) && \ (pidx > JH7110_CLK_SYS_END)) parents[i].hw = priv->pll[PLL_OF(pidx)]; + else if (pidx == JH7110_OSC) + parents[i].fw_name = "osc"; else if (pidx == JH7110_STG_APB) parents[i].fw_name = "stg_apb"; } diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c old mode 100644 new mode 100755 index cbcbc47..77c5b37 --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c @@ -14,6 +14,19 @@ #include #include "clk-starfive-jh7110.h" +/* sys external clocks */ +#define JH7110_OSC (JH7110_CLK_END + 0) +#define JH7110_GMAC1_RMII_REFIN (JH7110_CLK_END + 1) +#define JH7110_GMAC1_RGMII_RXIN (JH7110_CLK_END + 2) +#define JH7110_I2STX_BCLK_EXT (JH7110_CLK_END + 3) +#define JH7110_I2STX_LRCK_EXT (JH7110_CLK_END + 4) +#define JH7110_I2SRX_BCLK_EXT (JH7110_CLK_END + 5) +#define JH7110_I2SRX_LRCK_EXT (JH7110_CLK_END + 6) +#define JH7110_TDM_EXT (JH7110_CLK_END + 7) +#define JH7110_MCLK_EXT (JH7110_CLK_END + 8) +#define JH7110_JTAG_TCK_INNER (JH7110_CLK_END + 9) +#define JH7110_BIST_APB (JH7110_CLK_END + 10) + static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = { /*root*/ JH7110__MUX(JH7110_CPU_ROOT, "cpu_root", PARENT_NUMS_2, diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/starfive/clk-starfive-jh7110-vout.c index b565ffe..be38593 100755 --- a/drivers/clk/starfive/clk-starfive-jh7110-vout.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c @@ -23,6 +23,11 @@ #include #include "clk-starfive-jh7110.h" +/* external clocks */ +#define JH7110_HDMITX0_PIXELCLK (JH7110_CLK_VOUT_END + 0) +#define JH7110_MIPITX_DPHY_RXESC (JH7110_CLK_VOUT_END + 1) +#define JH7110_MIPITX_DPHY_TXBYTEHS (JH7110_CLK_VOUT_END + 2) + static const struct jh7110_clk_data jh7110_clk_vout_data[] __initconst = { //divider JH7110__DIV(JH7110_APB, "apb", 8, JH7110_DISP_AHB), diff --git a/include/dt-bindings/clock/starfive-jh7110-clkgen.h b/include/dt-bindings/clock/starfive-jh7110-clkgen.h index 0b8798a..e565523 100755 --- a/include/dt-bindings/clock/starfive-jh7110-clkgen.h +++ b/include/dt-bindings/clock/starfive-jh7110-clkgen.h @@ -370,25 +370,4 @@ #define JH7110_CLK_END 339 -/* sys external clocks */ -#define JH7110_OSC (JH7110_CLK_END + 0) -#define JH7110_GMAC1_RMII_REFIN (JH7110_CLK_END + 1) -#define JH7110_GMAC1_RGMII_RXIN (JH7110_CLK_END + 2) -#define JH7110_I2STX_BCLK_EXT (JH7110_CLK_END + 3) -#define JH7110_I2STX_LRCK_EXT (JH7110_CLK_END + 4) -#define JH7110_I2SRX_BCLK_EXT (JH7110_CLK_END + 5) -#define JH7110_I2SRX_LRCK_EXT (JH7110_CLK_END + 6) -#define JH7110_TDM_EXT (JH7110_CLK_END + 7) -#define JH7110_MCLK_EXT (JH7110_CLK_END + 8) -#define JH7110_JTAG_TCK_INNER (JH7110_CLK_END + 9) -#define JH7110_BIST_APB (JH7110_CLK_END + 10) - -/* stg external clocks */ -#define JH7110_STG_APB (JH7110_CLK_END + 11) - -/* aon external clocks */ -#define JH7110_GMAC0_RMII_REFIN (JH7110_CLK_END + 12) -#define JH7110_GMAC0_RGMII_RXIN (JH7110_CLK_END + 13) -#define JH7110_CLK_RTC (JH7110_CLK_END + 14) - #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */ diff --git a/include/dt-bindings/clock/starfive-jh7110-isp.h b/include/dt-bindings/clock/starfive-jh7110-isp.h index b4f2873..498d568 100755 --- a/include/dt-bindings/clock/starfive-jh7110-isp.h +++ b/include/dt-bindings/clock/starfive-jh7110-isp.h @@ -44,10 +44,4 @@ #define JH7110_CLK_ISP_END 30 -/* external clocks */ -#define JH7110_ISP_TOP_CLK_ISPCORE_2X_CLKGEN (JH7110_CLK_ISP_END + 0) -#define JH7110_ISP_TOP_CLK_ISP_AXI_CLKGEN (JH7110_CLK_ISP_END + 1) -#define JH7110_ISP_TOP_CLK_BIST_APB_CLKGEN (JH7110_CLK_ISP_END + 2) -#define JH7110_ISP_TOP_CLK_DVP_CLKGEN (JH7110_CLK_ISP_END + 3) - #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */ diff --git a/include/dt-bindings/clock/starfive-jh7110-vout.h b/include/dt-bindings/clock/starfive-jh7110-vout.h index e76a80a..9501cdb 100755 --- a/include/dt-bindings/clock/starfive-jh7110-vout.h +++ b/include/dt-bindings/clock/starfive-jh7110-vout.h @@ -56,11 +56,4 @@ #define JH7110_CLK_VOUT_END 41 -/* external clocks */ -#define JH7110_HDMITX0_PIXELCLK (JH7110_CLK_VOUT_END + 0) -#define JH7110_MIPITX_DPHY_RXESC (JH7110_CLK_VOUT_END + 1) -#define JH7110_MIPITX_DPHY_TXBYTEHS (JH7110_CLK_VOUT_END + 2) - - - #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */