From: Vinod Koul Date: Wed, 12 Jun 2013 08:09:57 +0000 (+0530) Subject: dmaengine: dw: select DW_DMAC_BIG_ENDIAN_IO automagically X-Git-Tag: v3.11-rc1~75^2~15 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e368b510c01aaf7b2957306836ffdeacc24712a3;p=profile%2Fcommon%2Fkernel-common.git dmaengine: dw: select DW_DMAC_BIG_ENDIAN_IO automagically Signed-off-by: Vinod Koul --- diff --git a/drivers/dma/dw/Kconfig b/drivers/dma/dw/Kconfig index db2b41f..dde1324 100644 --- a/drivers/dma/dw/Kconfig +++ b/drivers/dma/dw/Kconfig @@ -10,6 +10,7 @@ config DW_DMAC_CORE config DW_DMAC tristate "Synopsys DesignWare AHB DMA platform driver" select DW_DMAC_CORE + select DW_DMAC_BIG_ENDIAN_IO if AVR32 default y if CPU_AT32AP7000 help Support the Synopsys DesignWare AHB DMA controller. This @@ -25,12 +26,4 @@ config DW_DMAC_PCI Intel Medfield has integrated this GPDMA controller. config DW_DMAC_BIG_ENDIAN_IO - bool "Use big endian I/O register access" - default y if AVR32 - depends on DW_DMAC_CORE - help - Say yes here to use big endian I/O access when reading and writing - to the DMA controller registers. This is needed on some platforms, - like the Atmel AVR32 architecture. - - If unsure, use the default setting. + bool diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h index 07c5a6e..deb4274 100644 --- a/drivers/dma/dw/regs.h +++ b/drivers/dma/dw/regs.h @@ -101,6 +101,12 @@ struct dw_dma_regs { u32 DW_PARAMS; }; +/* + * Big endian I/O access when reading and writing to the DMA controller + * registers. This is needed on some platforms, like the Atmel AVR32 + * architecture. + */ + #ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO #define dma_readl_native ioread32be #define dma_writel_native iowrite32be