From: Dmitry Osipenko Date: Sun, 14 Nov 2021 22:07:58 +0000 (+0300) Subject: clk: tegra: Make vde a child of pll_p on tegra114 X-Git-Tag: v6.1-rc5~2162^2~5^2^2~1 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e360e116a0eec9cf719cda5860e95d36606687e7;p=platform%2Fkernel%2Flinux-starfive.git clk: tegra: Make vde a child of pll_p on tegra114 The current default is to leave the VDE clock's parent at the default, which is clk_m. However, that is not a configuration that will allow the VDE to function. Reparent it to pll_p instead to make sure the hardware can actually decode video content. Tested-by: Anton Bambura # ASUS TF701T Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index bc9e47a..ef718c4 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -1158,7 +1158,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0 }, { TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 }, { TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 }, - { TEGRA114_CLK_VDE, TEGRA114_CLK_CLK_MAX, 600000000, 0 }, + { TEGRA114_CLK_VDE, TEGRA114_CLK_PLL_P, 408000000, 0 }, { TEGRA114_CLK_SPDIF_IN_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 }, { TEGRA114_CLK_I2S0_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 }, { TEGRA114_CLK_I2S1_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },