From: william.qiu <william.qiu@starfivetech.com>
Date: Wed, 27 Apr 2022 10:04:03 +0000 (+0800)
Subject: dt-bingings:crypto: add crypto node for jh7110 soc.
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e3392a84723dc779f85906e4ae302cffd55f9c09;p=platform%2Fkernel%2Flinux-starfive.git

dt-bingings:crypto: add crypto node for jh7110 soc.

add support for jh7110 crypto.

Signed-off-by: william.qiu <william.qiu@starfivetech.com>
---

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index bd5028a..b7babe8 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -510,6 +510,40 @@
 			status = "disabled";
 		};
 
+		sec_dma: sec_dma@16008000 {
+			/*compatible = "arm,pl080", "arm,primecell";*/
+			compatible = "starfive,pl080";
+			reg = <0x0 0x16008000 0x0 0x4000>;
+			reg-names = "sec_dma";
+			interrupt-parent = <&plic>;
+			interrupts = <29>;
+			clocks = <&oscclk>;
+			clock-names = "apb_pclk";
+			lli-bus-interface-ahb1;
+			/*lli-bus-interface-ahb2;*/
+			mem-bus-interface-ahb1;
+			/*mem-bus-interface-ahb2;*/
+			memcpy-burst-size = <256>;
+			memcpy-bus-width = <32>;
+			#dma-cells = <2>;
+			/*status = "disabled";*/
+		};
+
+		crypto: crypto@16000000 {
+			compatible = "starfive,jh7110-sec";
+			reg = <0x0 0x16000000 0x0 0x4000>,
+			      <0x0 0x16008000 0x0 0x4000>;
+			reg-names = "secreg","secdma";
+			interrupts = <28>, <29>;
+			interrupt-names = "secirq",
+					"dmairq";
+			clocks = <&clkgen JH7110_SEC_HCLK>,
+					<&clkgen JH7110_SEC_MISCAHB_CLK>;
+			clock-names = "sec_hclk","sec_ahb";
+			resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
+			reset-names = "sec_hre";
+		};
+
 		i2c6: i2c@12060000 {
 			compatible = "snps,designware-i2c";
 			reg = <0x0 0x12060000 0x0 0x10000>;