From: Rob Herring Date: Tue, 12 May 2020 20:45:39 +0000 (-0500) Subject: spi: dt-bindings: sifive: Add missing 2nd register region X-Git-Tag: v5.10.7~2333^2~106 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e2f233ec155360d1cfff19cde77ffd4785d571da;p=platform%2Fkernel%2Flinux-rpi.git spi: dt-bindings: sifive: Add missing 2nd register region The 'reg' description and example have a 2nd register region for memory mapped flash, but the schema says there is only 1 region. Fix this. Cc: Palmer Dabbelt Cc: linux-spi@vger.kernel.org Cc: linux-riscv@lists.infradead.org Acked-by: Mark Brown Acked-by: Paul Walmsley Signed-off-by: Rob Herring --- diff --git a/Documentation/devicetree/bindings/spi/spi-sifive.yaml b/Documentation/devicetree/bindings/spi/spi-sifive.yaml index 28040598bfae..fb583e57c1f2 100644 --- a/Documentation/devicetree/bindings/spi/spi-sifive.yaml +++ b/Documentation/devicetree/bindings/spi/spi-sifive.yaml @@ -32,11 +32,10 @@ properties: https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi reg: - maxItems: 1 - - description: - Physical base address and size of SPI registers map - A second (optional) range can indicate memory mapped flash + minItems: 1 + items: + - description: SPI registers region + - description: Memory mapped flash region interrupts: maxItems: 1