From: Hyung-Kyu Choi Date: Thu, 8 Jun 2017 09:33:12 +0000 (+0900) Subject: [RyuJIT/ARM32] Unassign double register properly at BB entry X-Git-Tag: submit/tizen/20210909.063632~11030^2~6925^2~373^2~4 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e26fa75f904b3d1ef4ec7c889a957c2a17233082;p=platform%2Fupstream%2Fdotnet%2Fruntime.git [RyuJIT/ARM32] Unassign double register properly at BB entry When updating var locations at basic block entry, we should unassign double register properly for TYP_DOUBLE interval. Signed-off-by: Hyung-Kyu Choi Commit migrated from https://github.com/dotnet/coreclr/commit/02f11738345521f0f736333b278dd0d14d6cf3b7 --- diff --git a/src/coreclr/src/jit/lsra.cpp b/src/coreclr/src/jit/lsra.cpp index f496315..319195e 100644 --- a/src/coreclr/src/jit/lsra.cpp +++ b/src/coreclr/src/jit/lsra.cpp @@ -7005,15 +7005,21 @@ void LinearScan::processBlockStartLocations(BasicBlock* currentBlock, bool alloc // Is there another interval currently assigned to this register? If so unassign it. if (assignedInterval != nullptr) { +#ifdef _TARGET_ARM_ + if (assignedInterval->assignedReg == targetRegRecord || isSecondHalfReg(targetRegRecord, assignedInterval)) +#else if (assignedInterval->assignedReg == targetRegRecord) +#endif { + regNumber assignedRegNum = assignedInterval->assignedReg->regNum; + // If the interval is active, it will be set to active when we reach its new // register assignment (which we must not yet have done, or it wouldn't still be // assigned to this register). assignedInterval->isActive = false; - unassignPhysReg(targetRegRecord, nullptr); + unassignPhysReg(assignedInterval->assignedReg, nullptr); if (allocationPass && assignedInterval->isLocalVar && - inVarToRegMap[assignedInterval->getVarIndex(compiler)] == targetReg) + inVarToRegMap[assignedInterval->getVarIndex(compiler)] == assignedRegNum) { inVarToRegMap[assignedInterval->getVarIndex(compiler)] = REG_STK; }