From: Matthias Braun <matze@braunis.de>
Date: Tue, 3 May 2016 04:54:16 +0000 (+0000)
Subject: AArch64/optimizeCondBranch: Remove earlier kill flag when forming TBZ
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e25bbd0bb82bb6fe2c04d0789d7896ea24086166;p=platform%2Fupstream%2Fllvm.git

AArch64/optimizeCondBranch: Remove earlier kill flag when forming TBZ

This fixes -verify-machineinstrs complaints when compiling
test-suite/SingleSource/Benchmarks/Shootout-C++/wordfreq.cpp

llvm-svn: 268360
---

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index f152854..46d90ab 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -3888,6 +3888,8 @@ bool AArch64InstrInfo::optimizeCondBranch(MachineInstr *MI) const {
                               .addReg(NewReg)
                               .addImm(Imm)
                               .addMBB(TBB);
+    // Register lives on to the CBZ now.
+    MO.setIsKill(false);
 
     // For immediate smaller than 32, we need to use the 32-bit
     // variant (W) in all cases. Indeed the 64-bit variant does not
diff --git a/llvm/test/CodeGen/AArch64/optimize-cond-branch.ll b/llvm/test/CodeGen/AArch64/optimize-cond-branch.ll
new file mode 100644
index 0000000..ef6e31b
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/optimize-cond-branch.ll
@@ -0,0 +1,48 @@
+; RUN: llc -verify-machineinstrs -o - %s | FileCHeck %s
+target triple = "arm64--"
+
+; AArch64InstrInfo::optimizeCondBranch() optimizes the
+; "x = and y, 256; cmp x, 0; br" from an "and; cbnz" to a tbnz instruction.
+; It forgot to clear the a flag resulting in a MachineVerifier complaint.
+;
+; Writing a stable/simple test is tricky since most tbz instructions are already
+; formed in SelectionDAG, optimizeCondBranch() only triggers if the and
+; instruction is in a different block than the conditional jump.
+;
+; CHECK-LABEL: func
+; CHECK-NOT: and
+; CHECK: tbnz
+define void @func() {
+  %c0 = icmp sgt i64 0, 0
+  br i1 %c0, label %b1, label %b6
+
+b1:
+  br i1 undef, label %b3, label %b2
+
+b2:
+  %v0 = tail call i32 @extfunc()
+  br label %b5
+
+b3:
+  %v1 = load i32, i32* undef, align 4
+  %v2 = and i32 %v1, 256
+  br label %b5
+
+b5:
+  %v3 = phi i32 [ %v2, %b3 ], [ %v0, %b2 ]
+  %c1 = icmp eq i32 %v3, 0
+  br i1 %c1, label %b8, label %b7
+
+b6:
+  tail call i32 @extfunc()
+  ret void
+
+b7:
+  tail call i32 @extfunc()
+  ret void
+
+b8:
+  ret void
+}
+
+declare i32 @extfunc()