From: Artyom Tarasenko <atar4qemu@googlemail.com>
Date: Sun, 13 Dec 2009 13:30:44 +0000 (+0000)
Subject: fdc/sparc32: don't hang on detection under OBP
X-Git-Tag: TizenStudio_2.0_p2.3~6282
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e1edf2296c617536610a8a29af18229ebe6327c5;p=sdk%2Femulator%2Fqemu.git

fdc/sparc32: don't hang on detection under OBP

Stepping through the SS-5's OBP initialization routines
it looks like reading fdc main status register should
clear the fd interrupt.
The patch doesn't fix problems with fdc on sparc platform,
it only fixes fdc detection.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---

diff --git a/hw/fdc.c b/hw/fdc.c
index e875291..11ea439 100644
--- a/hw/fdc.c
+++ b/hw/fdc.c
@@ -960,6 +960,12 @@ static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
     fdctrl->dsr &= ~FD_DSR_PWRDOWN;
     fdctrl->dor |= FD_DOR_nRESET;
 
+    /* Sparc mutation */
+    if (fdctrl->sun4m) {
+        retval |= FD_MSR_DIO;
+        fdctrl_reset_irq(fdctrl);
+    };
+
     FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
 
     return retval;