From: Simon Pilgrim Date: Wed, 8 Feb 2023 16:12:01 +0000 (+0000) Subject: [X86] Merge DQ/BW AVX512 ISD::ABDS/ABDU setOperationAction calls. NFCI. X-Git-Tag: upstream/17.0.6~18177 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e1b5014119c027bff4d2784c18d5d1fda3676f13;p=platform%2Fupstream%2Fllvm.git [X86] Merge DQ/BW AVX512 ISD::ABDS/ABDU setOperationAction calls. NFCI. All set to Custom - there's no need to have them in separate loops --- diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 55110e6..4300fa4 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1816,6 +1816,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::ROTL, VT, Custom); setOperationAction(ISD::ROTR, VT, Custom); setOperationAction(ISD::SETCC, VT, Custom); + setOperationAction(ISD::ABDS, VT, Custom); + setOperationAction(ISD::ABDU, VT, Custom); // The condition codes aren't legal in SSE/AVX and under AVX512 we use // setcc all the way to isel and prefer SETGT in some isel patterns. @@ -1828,8 +1830,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::SMIN, VT, Legal); setOperationAction(ISD::UMIN, VT, Legal); setOperationAction(ISD::ABS, VT, Legal); - setOperationAction(ISD::ABDS, VT, Custom); - setOperationAction(ISD::ABDU, VT, Custom); setOperationAction(ISD::CTPOP, VT, Custom); setOperationAction(ISD::STRICT_FSETCC, VT, Custom); setOperationAction(ISD::STRICT_FSETCCS, VT, Custom); @@ -1837,8 +1837,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, for (auto VT : { MVT::v64i8, MVT::v32i16 }) { setOperationAction(ISD::ABS, VT, HasBWI ? Legal : Custom); - setOperationAction(ISD::ABDS, VT, Custom); - setOperationAction(ISD::ABDU, VT, Custom); setOperationAction(ISD::CTPOP, VT, Subtarget.hasBITALG() ? Legal : Custom); setOperationAction(ISD::CTLZ, VT, Custom); setOperationAction(ISD::SMAX, VT, HasBWI ? Legal : Custom);