From: Sumanth Gundapaneni Date: Wed, 18 Oct 2017 18:07:07 +0000 (+0000) Subject: [Hexagon] New HVX target features. X-Git-Tag: llvmorg-6.0.0-rc1~5367 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e1983bcf552980433a7a8ed7a2ae31ded4ae9b4a;p=platform%2Fupstream%2Fllvm.git [Hexagon] New HVX target features. This patch lets the llvm tools handle the new HVX target features that are added by frontend (clang). The target-features are of the form "hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX. "hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated. The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}. Eg: "+hvxv62" For the correct HVX code generation, the user must use the following target features. For 64B mode: "+hvxv62" "+hvx-length64b" For 128B mode: "+hvxv62" "+hvx-length128b" Clang picks a default length if none is specified. If for some reason, no hvx-length is specified to llvm, the compilation will bail out. There is a corresponding clang patch. Differential Revision: https://reviews.llvm.org/D38851 llvm-svn: 316101 --- diff --git a/llvm/lib/Target/Hexagon/Hexagon.td b/llvm/lib/Target/Hexagon/Hexagon.td index 0c1ff96..23221a9 100644 --- a/llvm/lib/Target/Hexagon/Hexagon.td +++ b/llvm/lib/Target/Hexagon/Hexagon.td @@ -25,10 +25,31 @@ include "llvm/Target/Target.td" include "HexagonDepArch.td" // Hexagon ISA Extensions -def ExtensionHVX: SubtargetFeature<"hvx", "UseHVXOps", "true", - "Hexagon HVX instructions">; -def ExtensionHVXDbl: SubtargetFeature<"hvx-double", "UseHVXDblOps", "true", - "Hexagon HVX Double instructions">; +def ExtensionHVXV60: SubtargetFeature<"hvxv60", "HexagonHVXVersion", + "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">; +def ExtensionHVXV62: SubtargetFeature<"hvxv62", "HexagonHVXVersion", + "Hexagon::ArchEnum::V62", "Hexagon HVX instructions", + [ExtensionHVXV60]>; +def ExtensionHVX: SubtargetFeature<"hvx", "HexagonHVXVersion", + "Hexagon::ArchEnum::V62", "Hexagon HVX instructions", + [ExtensionHVXV60, + ExtensionHVXV62]>; +def ExtensionHVX64B + : SubtargetFeature<"hvx-length64b", "UseHVX64BOps", "true", + "Hexagon HVX 64B instructions", + [ExtensionHVXV60, ExtensionHVXV62]>; +def ExtensionHVX128B + : SubtargetFeature<"hvx-length128b", "UseHVX128BOps", "true", + "Hexagon HVX 128B instructions", + [ExtensionHVXV60, ExtensionHVXV62]>; + +// This is an alias to ExtensionHVX128B to accept the hvx-double as +// an acceptable subtarget feature. +def ExtensionHVXDbl + : SubtargetFeature<"hvx-double", "UseHVX128BOps", "true", + "Hexagon HVX 128B instructions", + [ExtensionHVXV60, ExtensionHVXV62]>; + def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true", "Use constant-extended calls">; @@ -38,14 +59,21 @@ def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true", def UseMEMOP : Predicate<"HST->useMemOps()">; def IEEERndNearV5T : Predicate<"HST->modeIEEERndNear()">; -def UseHVXDbl : Predicate<"HST->useHVXDblOps()">, - AssemblerPredicate<"ExtensionHVXDbl">; -def UseHVXSgl : Predicate<"HST->useHVXSglOps()">; -def UseHVX : Predicate<"HST->useHVXSglOps() ||HST->useHVXDblOps()">, - AssemblerPredicate<"ExtensionHVX">; - -def Hvx64 : HwMode<"+hvx,-hvx-double">; -def Hvx128 : HwMode<"+hvx,+hvx-double">; +def UseHVX64B : Predicate<"HST->useHVX64BOps()">, + AssemblerPredicate<"ExtensionHVX64B">; +def UseHVX128B : Predicate<"HST->useHVX128BOps()">, + AssemblerPredicate<"ExtensionHVX128B">; +def UseHVX : Predicate<"HST->useHVXOps()">, + AssemblerPredicate<"ExtensionHVXV60">; +def UseHVXV60 : Predicate<"HST->useHVXOps()">, + AssemblerPredicate<"ExtensionHVXV60">; +def UseHVXV62 : Predicate<"HST->useHVXOps()">, + AssemblerPredicate<"ExtensionHVXV62">; + +def Hvx64 : HwMode<"+hvx-length64b">; +def Hvx64old : HwMode<"-hvx-double">; +def Hvx128 : HwMode<"+hvx-length128b">; +def Hvx128old : HwMode<"+hvx-double">; //===----------------------------------------------------------------------===// // Classes used for relation maps. @@ -274,9 +302,9 @@ def : Proc<"hexagonv5", HexagonModelV4, def : Proc<"hexagonv55", HexagonModelV55, [ArchV4, ArchV5, ArchV55]>; def : Proc<"hexagonv60", HexagonModelV60, - [ArchV4, ArchV5, ArchV55, ArchV60, ExtensionHVX]>; + [ArchV4, ArchV5, ArchV55, ArchV60]>; def : Proc<"hexagonv62", HexagonModelV62, - [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, ExtensionHVX]>; + [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62]>; //===----------------------------------------------------------------------===// // Declare the target which we are implementing diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index d9d8dbe..957fc8ca 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -357,7 +357,7 @@ static bool CC_HexagonVector(unsigned ValNo, MVT ValVT, auto &MF = State.getMachineFunction(); auto &HST = MF.getSubtarget(); - if (HST.useHVXSglOps() && + if (HST.useHVX64BOps() && (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || LocVT == MVT::v64i8 || LocVT == MVT::v512i1)) { if (unsigned Reg = State.AllocateReg(VecLstS)) { @@ -368,7 +368,7 @@ static bool CC_HexagonVector(unsigned ValNo, MVT ValVT, State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); return false; } - if (HST.useHVXSglOps() && (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || + if (HST.useHVX64BOps() && (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || LocVT == MVT::v128i8)) { if (unsigned Reg = State.AllocateReg(VecLstD)) { State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); @@ -379,8 +379,8 @@ static bool CC_HexagonVector(unsigned ValNo, MVT ValVT, return false; } // 128B Mode - if (HST.useHVXDblOps() && (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || - LocVT == MVT::v128i16 || LocVT == MVT::v256i8)) { + if (HST.useHVX128BOps() && (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || + LocVT == MVT::v128i16 || LocVT == MVT::v256i8)) { if (unsigned Reg = State.AllocateReg(VecLstD)) { State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); return false; @@ -389,7 +389,7 @@ static bool CC_HexagonVector(unsigned ValNo, MVT ValVT, State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); return false; } - if (HST.useHVXDblOps() && + if (HST.useHVX128BOps() && (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) { if (unsigned Reg = State.AllocateReg(VecLstS)) { @@ -437,7 +437,7 @@ static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT, LocInfo = CCValAssign::Full; } else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 || LocVT == MVT::v32i32 || LocVT == MVT::v16i64 || - (LocVT == MVT::v1024i1 && HST.useHVXDblOps())) { + (LocVT == MVT::v1024i1 && HST.useHVX128BOps())) { LocVT = MVT::v32i32; ValVT = MVT::v32i32; LocInfo = CCValAssign::Full; @@ -507,7 +507,7 @@ static bool RetCC_HexagonVector(unsigned ValNo, MVT ValVT, return false; } } else if (LocVT == MVT::v32i32) { - unsigned Req = HST.useHVXDblOps() ? Hexagon::V0 : Hexagon::W0; + unsigned Req = HST.useHVX128BOps() ? Hexagon::V0 : Hexagon::W0; if (unsigned Reg = State.AllocateReg(Req)) { State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); return false; @@ -827,9 +827,9 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, DEBUG(dbgs() << "Function needs byte stack align due to call args\n"); // V6 vectors passed by value have 64 or 128 byte alignment depending // on whether we are 64 byte vector mode or 128 byte. - bool UseHVXDbl = Subtarget.useHVXDblOps(); + bool UseHVX128B = Subtarget.useHVX128BOps(); assert(Subtarget.useHVXOps()); - const unsigned ObjAlign = UseHVXDbl ? 128 : 64; + const unsigned ObjAlign = UseHVX128B ? 128 : 64; LargestAlignSeen = std::max(LargestAlignSeen, ObjAlign); MFI.ensureMaxAlignment(LargestAlignSeen); } @@ -940,15 +940,15 @@ static bool getIndexedAddressParts(SDNode *Ptr, EVT VT, auto &HST = static_cast(DAG.getSubtarget()); - bool ValidHVXDblType = - HST.useHVXDblOps() && (VT == MVT::v32i32 || VT == MVT::v16i64 || - VT == MVT::v64i16 || VT == MVT::v128i8); + bool ValidHVX128BType = + HST.useHVX128BOps() && (VT == MVT::v32i32 || VT == MVT::v16i64 || + VT == MVT::v64i16 || VT == MVT::v128i8); bool ValidHVXType = - HST.useHVXSglOps() && (VT == MVT::v16i32 || VT == MVT::v8i64 || + HST.useHVX64BOps() && (VT == MVT::v16i32 || VT == MVT::v8i64 || VT == MVT::v32i16 || VT == MVT::v64i8); - if (ValidHVXDblType || ValidHVXType || - VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { + if (ValidHVX128BType || ValidHVXType || VT == MVT::i64 || VT == MVT::i32 || + VT == MVT::i16 || VT == MVT::i8) { IsInc = (Ptr->getOpcode() == ISD::ADD); Base = Ptr->getOperand(0); Offset = Ptr->getOperand(1); @@ -1182,7 +1182,7 @@ SDValue HexagonTargetLowering::LowerFormalArguments( RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); - } else if (Subtarget.useHVXDblOps() && + } else if (Subtarget.useHVX128BOps() && ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 || RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) { unsigned VReg = @@ -1197,7 +1197,7 @@ SDValue HexagonTargetLowering::LowerFormalArguments( RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); - } else if (Subtarget.useHVXDblOps() && + } else if (Subtarget.useHVX128BOps() && ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 || RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) { unsigned VReg = @@ -1743,7 +1743,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, } if (Subtarget.hasV60TOps()) { - if (Subtarget.useHVXSglOps()) { + if (Subtarget.useHVX64BOps()) { addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass); @@ -1753,7 +1753,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass); addRegisterClass(MVT::v16i64, &Hexagon::HvxWRRegClass); addRegisterClass(MVT::v512i1, &Hexagon::HvxQRRegClass); - } else if (Subtarget.useHVXDblOps()) { + } else if (Subtarget.useHVX128BOps()) { addRegisterClass(MVT::v128i8, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v64i16, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v32i32, &Hexagon::HvxVRRegClass); @@ -1992,7 +1992,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); if (Subtarget.useHVXOps()) { - if (Subtarget.useHVXSglOps()) { + if (Subtarget.useHVX64BOps()) { setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i8, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i16, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i32, Custom); @@ -2004,7 +2004,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v64i8, Custom); setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i16, Custom); setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i32, Custom); - } else if (Subtarget.useHVXDblOps()) { + } else if (Subtarget.useHVX128BOps()) { setOperationAction(ISD::CONCAT_VECTORS, MVT::v256i8, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i16, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i32, Custom); @@ -2082,13 +2082,13 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, setIndexedStoreAction(ISD::POST_INC, VT, Legal); } - if (Subtarget.useHVXSglOps()) { + if (Subtarget.useHVX64BOps()) { for (MVT VT : {MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64}) { setIndexedLoadAction(ISD::POST_INC, VT, Legal); setIndexedStoreAction(ISD::POST_INC, VT, Legal); } - } else if (Subtarget.useHVXDblOps()) { + } else if (Subtarget.useHVX128BOps()) { for (MVT VT : {MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64, MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v32i64}) { setIndexedLoadAction(ISD::POST_INC, VT, Legal); @@ -2353,8 +2353,8 @@ HexagonTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) size_t MaskLen = Mask.size(); unsigned SizeInBits = VT.getScalarSizeInBits() * MaskLen; - if ((Subtarget.useHVXSglOps() && SizeInBits == 64 * 8) || - (Subtarget.useHVXDblOps() && SizeInBits == 128 * 8)) { + if ((Subtarget.useHVX64BOps() && SizeInBits == 64 * 8) || + (Subtarget.useHVX128BOps() && SizeInBits == 128 * 8)) { StridedLoadKind Pattern = isStridedLoad(Mask); if (Pattern == StridedLoadKind::NoPattern) return SDValue(); @@ -2617,11 +2617,11 @@ HexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op, return DAG.getNode(HexagonISD::COMBINE, dl, VT, Op.getOperand(1), Vec0); if (UseHVX) { - assert((Width == 64*8 && Subtarget.useHVXSglOps()) || - (Width == 128*8 && Subtarget.useHVXDblOps())); + assert((Width == 64 * 8 && Subtarget.useHVX64BOps()) || + (Width == 128 * 8 && Subtarget.useHVX128BOps())); SDValue Vec1 = Op.getOperand(1); - MVT OpTy = Subtarget.useHVXSglOps() ? MVT::v16i32 : MVT::v32i32; - MVT ReTy = Subtarget.useHVXSglOps() ? MVT::v32i32 : MVT::v64i32; + MVT OpTy = Subtarget.useHVX64BOps() ? MVT::v16i32 : MVT::v32i32; + MVT ReTy = Subtarget.useHVX64BOps() ? MVT::v32i32 : MVT::v64i32; SDValue B0 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec0); SDValue B1 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec1); SDValue VC = DAG.getNode(HexagonISD::VCOMBINE, dl, ReTy, B1, B0); @@ -2667,7 +2667,7 @@ HexagonTargetLowering::LowerEXTRACT_SUBVECTOR_HVX(SDValue Op, EVT VT = Op.getOperand(0).getValueType(); SDLoc dl(Op); bool UseHVX = Subtarget.useHVXOps(); - bool UseHVXSgl = Subtarget.useHVXSglOps(); + bool UseHVX64B = Subtarget.useHVX64BOps(); // Just in case... if (!VT.isVector() || !UseHVX) @@ -2675,7 +2675,7 @@ HexagonTargetLowering::LowerEXTRACT_SUBVECTOR_HVX(SDValue Op, EVT ResVT = Op.getValueType(); unsigned ResSize = ResVT.getSizeInBits(); - unsigned VectorSizeInBits = UseHVXSgl ? (64 * 8) : (128 * 8); + unsigned VectorSizeInBits = UseHVX64B ? (64 * 8) : (128 * 8); unsigned OpSize = VT.getSizeInBits(); // We deal only with cases where the result is the vector size @@ -3001,7 +3001,7 @@ HexagonTargetLowering::getRegForInlineAsmConstraint( case 512: return std::make_pair(0U, &Hexagon::HvxVRRegClass); case 1024: - if (Subtarget.hasV60TOps() && Subtarget.useHVXDblOps()) + if (Subtarget.hasV60TOps() && Subtarget.useHVX128BOps()) return std::make_pair(0U, &Hexagon::HvxVRRegClass); return std::make_pair(0U, &Hexagon::HvxWRRegClass); case 2048: @@ -3204,7 +3204,7 @@ HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI, case MVT::v32i32: case MVT::v16i64: if (Subtarget.hasV60TOps() && Subtarget.useHVXOps() && - Subtarget.useHVXDblOps()) + Subtarget.useHVX128BOps()) RRC = &Hexagon::HvxVRRegClass; else RRC = &Hexagon::HvxWRRegClass; diff --git a/llvm/lib/Target/Hexagon/HexagonPseudo.td b/llvm/lib/Target/Hexagon/HexagonPseudo.td index 199148f..b2d6631 100644 --- a/llvm/lib/Target/Hexagon/HexagonPseudo.td +++ b/llvm/lib/Target/Hexagon/HexagonPseudo.td @@ -427,7 +427,7 @@ class LDrivv_template def PS_vloadrw_ai: LDrivv_template, Requires<[HasV60T,UseHVX]>; def PS_vloadrw_nt_ai: LDrivv_template, - Requires<[HasV60T,UseHVXSgl]>; + Requires<[HasV60T,UseHVX]>; def PS_vloadrwu_ai: LDrivv_template, Requires<[HasV60T,UseHVX]>; diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td index b2e952a..51ef37f 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td @@ -216,25 +216,33 @@ let Namespace = "Hexagon" in { // HVX types -def VecI1 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v512i1, v1024i1, v512i1]>; -def VecI8 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v64i8, v128i8, v64i8]>; -def VecI16 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v32i16, v64i16, v32i16]>; -def VecI32 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v16i32, v32i32, v16i32]>; -def VecI64 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v8i64, v16i64, v8i64]>; -def VecPI8 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v128i8, v256i8, v128i8]>; -def VecPI16 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v64i16, v128i16, v64i16]>; -def VecPI32 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v32i32, v64i32, v32i32]>; -def VecPI64 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v16i64, v32i64, v16i64]>; - +def VecI1 + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], + [v512i1, v512i1, v1024i1, v1024i1, v512i1]>; +def VecI8 + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], + [v64i8, v64i8, v128i8, v128i8, v64i8]>; +def VecI16 + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], + [v32i16, v32i16, v64i16, v64i16, v32i16]>; +def VecI32 + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], + [v16i32, v16i32, v32i32, v32i32, v16i32]>; +def VecI64 + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], + [v8i64, v8i64, v16i64, v16i64, v8i64]>; +def VecPI8 + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], + [v128i8, v128i8, v256i8, v256i8, v128i8]>; +def VecPI16 + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], + [v64i16, v64i16, v128i16, v128i16, v64i16]>; +def VecPI32 + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], + [v32i32, v32i32, v64i32, v64i32, v32i32]>; +def VecPI64 + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], + [v16i64, v16i64, v32i64, v32i64, v16i64]>; // Register classes. // diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp index 2c6e340..7ec4c34 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -53,14 +53,6 @@ static cl::opt EnableIEEERndNear("enable-hexagon-ieee-rnd-near", static cl::opt EnableBSBSched("enable-bsb-sched", cl::Hidden, cl::ZeroOrMore, cl::init(true)); -static cl::opt EnableHexagonHVXDouble("enable-hexagon-hvx-double", - cl::Hidden, cl::ZeroOrMore, cl::init(false), - cl::desc("Enable Hexagon Double Vector eXtensions")); - -static cl::opt EnableHexagonHVX("enable-hexagon-hvx", - cl::Hidden, cl::ZeroOrMore, cl::init(false), - cl::desc("Enable Hexagon Vector eXtensions")); - static cl::opt EnableTCLatencySched("enable-tc-latency-sched", cl::Hidden, cl::ZeroOrMore, cl::init(false)); @@ -126,8 +118,8 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { else llvm_unreachable("Unrecognized Hexagon processor version"); - UseHVXOps = false; - UseHVXDblOps = false; + UseHVX128BOps = false; + UseHVX64BOps = false; UseLongCalls = false; UseMemOps = DisableMemOps ? false : EnableMemOps; @@ -136,10 +128,6 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { ParseSubtargetFeatures(CPUString, FS); - if (EnableHexagonHVX.getPosition()) - UseHVXOps = EnableHexagonHVX; - if (EnableHexagonHVXDouble.getPosition()) - UseHVXDblOps = EnableHexagonHVXDouble; if (OverrideLongCalls.getPosition()) UseLongCalls = OverrideLongCalls; diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/llvm/lib/Target/Hexagon/HexagonSubtarget.h index 9722852..54cf8e1 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.h +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.h @@ -46,12 +46,13 @@ class Triple; class HexagonSubtarget : public HexagonGenSubtargetInfo { virtual void anchor(); - bool UseMemOps, UseHVXOps, UseHVXDblOps; + bool UseMemOps, UseHVX64BOps, UseHVX128BOps; bool UseLongCalls; bool ModeIEEERndNear; public: Hexagon::ArchEnum HexagonArchVersion; + Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::V4; /// True if the target should use Back-Skip-Back scheduling. This is the /// default for V60. bool UseBSBScheduling; @@ -138,9 +139,9 @@ public: } bool modeIEEERndNear() const { return ModeIEEERndNear; } - bool useHVXOps() const { return UseHVXOps; } - bool useHVXDblOps() const { return UseHVXOps && UseHVXDblOps; } - bool useHVXSglOps() const { return UseHVXOps && !UseHVXDblOps; } + bool useHVXOps() const { return HexagonHVXVersion > Hexagon::ArchEnum::V4; } + bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; } + bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; } bool useLongCalls() const { return UseLongCalls; } bool usePredicatedCalls() const; diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index 05bbf39..6f48169 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -288,7 +288,7 @@ MCSubtargetInfo *Hexagon_MC::createHexagonMCSubtargetInfo(const Triple &TT, } MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName, ArchFS); - if (X->getFeatureBits()[Hexagon::ExtensionHVXDbl]) { + if (X->getFeatureBits()[Hexagon::ExtensionHVX128B]) { llvm::FeatureBitset Features = X->getFeatureBits(); X->setFeatureBits(Features.set(Hexagon::ExtensionHVX)); } diff --git a/llvm/test/CodeGen/Hexagon/SUnit-boundary-prob.ll b/llvm/test/CodeGen/Hexagon/SUnit-boundary-prob.ll index 9df178f..badab168 100644 --- a/llvm/test/CodeGen/Hexagon/SUnit-boundary-prob.ll +++ b/llvm/test/CodeGen/Hexagon/SUnit-boundary-prob.ll @@ -187,7 +187,7 @@ entry: } attributes #0 = { nounwind readnone } -attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #2 = { nounwind } !llvm.module.flags = !{!0} diff --git a/llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll b/llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll index 87d535f..30d18b7 100644 --- a/llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll +++ b/llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll @@ -30,4 +30,4 @@ b9: ; preds = %b6, %b4 ret i32 %v10 } -attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" } +attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" "target-features"="-hvxv60,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/bit-bitsplit-src.ll b/llvm/test/CodeGen/Hexagon/bit-bitsplit-src.ll index 2d1c71c..edac4cb 100644 --- a/llvm/test/CodeGen/Hexagon/bit-bitsplit-src.ll +++ b/llvm/test/CodeGen/Hexagon/bit-bitsplit-src.ll @@ -32,4 +32,4 @@ b0: ; Function Attrs: nounwind declare void @printf(i8* nocapture readonly, ...) local_unnamed_addr #0 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/bit-bitsplit.ll b/llvm/test/CodeGen/Hexagon/bit-bitsplit.ll index 4ae2e4e..52ae69a 100644 --- a/llvm/test/CodeGen/Hexagon/bit-bitsplit.ll +++ b/llvm/test/CodeGen/Hexagon/bit-bitsplit.ll @@ -14,4 +14,4 @@ entry: ret i32 %and2 } -attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" } +attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx" } diff --git a/llvm/test/CodeGen/Hexagon/bit-ext-sat.ll b/llvm/test/CodeGen/Hexagon/bit-ext-sat.ll index 47c49c23..713e398 100644 --- a/llvm/test/CodeGen/Hexagon/bit-ext-sat.ll +++ b/llvm/test/CodeGen/Hexagon/bit-ext-sat.ll @@ -53,5 +53,5 @@ declare i32 @llvm.hexagon.A2.sath(i32) #1 declare i32 @llvm.hexagon.A2.satub(i32) #1 declare i32 @llvm.hexagon.A2.satuh(i32) #1 -attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/bit-extract-off.ll b/llvm/test/CodeGen/Hexagon/bit-extract-off.ll index 183435a..4086ca3 100644 --- a/llvm/test/CodeGen/Hexagon/bit-extract-off.ll +++ b/llvm/test/CodeGen/Hexagon/bit-extract-off.ll @@ -19,5 +19,5 @@ b5: ; preds = %b5, %b4 declare double @fabs(double) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } -attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } +attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/bit-extract.ll b/llvm/test/CodeGen/Hexagon/bit-extract.ll index ad7d05d..33fa50c 100644 --- a/llvm/test/CodeGen/Hexagon/bit-extract.ll +++ b/llvm/test/CodeGen/Hexagon/bit-extract.ll @@ -72,4 +72,4 @@ entry: ret i32 %bf.ashr } -attributes #0 = { noinline norecurse nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { noinline norecurse nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/bit-has.ll b/llvm/test/CodeGen/Hexagon/bit-has.ll index 9022de3..5bb0f2f 100644 --- a/llvm/test/CodeGen/Hexagon/bit-has.ll +++ b/llvm/test/CodeGen/Hexagon/bit-has.ll @@ -60,5 +60,5 @@ b23: ; preds = %b21 declare i32 @llvm.hexagon.A2.sath(i32) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-long-calls" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll b/llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll index db57998..e7dd87c 100644 --- a/llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll +++ b/llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll @@ -24,7 +24,7 @@ for.end: ; preds = %for.body, %entry declare hidden i64 @danny(i32*, i32* nocapture readonly dereferenceable(4)) #1 align 2 declare hidden i32 @sammy(i32* nocapture, i32) #0 align 2 -attributes #0 = { nounwind optsize "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind optsize readonly "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind optsize "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind optsize readonly "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #2 = { optsize } diff --git a/llvm/test/CodeGen/Hexagon/bit-rie.ll b/llvm/test/CodeGen/Hexagon/bit-rie.ll index 302382a..a090a66 100644 --- a/llvm/test/CodeGen/Hexagon/bit-rie.ll +++ b/llvm/test/CodeGen/Hexagon/bit-rie.ll @@ -190,7 +190,7 @@ declare i64 @llvm.hexagon.M2.mpyd.ll.s1(i32, i32) #2 declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind } attributes #2 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/bitconvert-vector.ll b/llvm/test/CodeGen/Hexagon/bitconvert-vector.ll index c090721..a89a15c 100644 --- a/llvm/test/CodeGen/Hexagon/bitconvert-vector.ll +++ b/llvm/test/CodeGen/Hexagon/bitconvert-vector.ll @@ -24,4 +24,4 @@ entry: attributes #0 = { nounwind readnone } -attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } diff --git a/llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll b/llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll index 1d06953..7efc38f 100644 --- a/llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll +++ b/llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll @@ -17,5 +17,5 @@ entry: ; Function Attrs: nounwind readnone declare <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32>) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/builtin-expect.ll b/llvm/test/CodeGen/Hexagon/builtin-expect.ll index 9945da1..9fed287 100644 --- a/llvm/test/CodeGen/Hexagon/builtin-expect.ll +++ b/llvm/test/CodeGen/Hexagon/builtin-expect.ll @@ -39,6 +39,6 @@ b14: ; preds = %b13, %b10 declare i32 @bar(i32) local_unnamed_addr #0 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b,-long-calls" } !0 = !{!"branch_weights", i32 1, i32 2000} diff --git a/llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll b/llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll index be234aa..2d65a5c 100644 --- a/llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll +++ b/llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll @@ -68,4 +68,4 @@ b19: ; preds = %b4 unreachable } -attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/cfi-offset.ll b/llvm/test/CodeGen/Hexagon/cfi-offset.ll index 100034a0..c7d447d 100644 --- a/llvm/test/CodeGen/Hexagon/cfi-offset.ll +++ b/llvm/test/CodeGen/Hexagon/cfi-offset.ll @@ -39,5 +39,5 @@ declare i8* @__cxa_begin_catch(i8*) declare void @__cxa_end_catch() -attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/Hexagon/common-gep-inbounds.ll b/llvm/test/CodeGen/Hexagon/common-gep-inbounds.ll index a8b7572..ddc73c2 100644 --- a/llvm/test/CodeGen/Hexagon/common-gep-inbounds.ll +++ b/llvm/test/CodeGen/Hexagon/common-gep-inbounds.ll @@ -17,4 +17,4 @@ entry: ret i16 %a } -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/const-pool-tf.ll b/llvm/test/CodeGen/Hexagon/const-pool-tf.ll index 9a4569b..e678925 100644 --- a/llvm/test/CodeGen/Hexagon/const-pool-tf.ll +++ b/llvm/test/CodeGen/Hexagon/const-pool-tf.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic < %s | FileCheck %s +; RUN: opt -relocation-model pic -march=hexagon -mcpu=hexagonv60 -O2 -S < %s | llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic -; CHECK: @PCREL +; CHECK: jumpr target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/convert-to-dot-old.ll b/llvm/test/CodeGen/Hexagon/convert-to-dot-old.ll index b793fa0..c4e67f3 100644 --- a/llvm/test/CodeGen/Hexagon/convert-to-dot-old.ll +++ b/llvm/test/CodeGen/Hexagon/convert-to-dot-old.ll @@ -103,8 +103,8 @@ declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #2 declare i32 @llvm.hexagon.A2.aslh(i32) #2 declare void @foo(i16*, i32*, i16*, i16 signext, i16 signext, i16 signext) local_unnamed_addr #3 -attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" } attributes #1 = { argmemonly nounwind } attributes #2 = { nounwind readnone } -attributes #3 = { optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #3 = { optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" } attributes #4 = { nounwind optsize } diff --git a/llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll b/llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll index 35c12f1..62beeee 100644 --- a/llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll +++ b/llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll @@ -14,4 +14,4 @@ entry: declare <32 x i32> @llvm.hexagon.V6.vrdelta.128B(<32 x i32>, <32 x i32>) declare <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1>, <32 x i32>, <32 x i32>) -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } diff --git a/llvm/test/CodeGen/Hexagon/dead-store-stack.ll b/llvm/test/CodeGen/Hexagon/dead-store-stack.ll index 0d8124e..532c2b2 100644 --- a/llvm/test/CodeGen/Hexagon/dead-store-stack.ll +++ b/llvm/test/CodeGen/Hexagon/dead-store-stack.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -march=hexagon -mcpu=hexagonv62< %s | FileCheck %s ; CHECK: ParseFunc: ; CHECK: r[[ARG0:[0-9]+]] = memuh(r[[ARG1:[0-9]+]]+#[[OFFSET:[0-9]+]]) ; CHECK: memw(r[[ARG1]]+#[[OFFSET]]) = r[[ARG0]] @@ -126,6 +126,7 @@ sw.epilog: ; Function Attrs: nounwind declare void @snprintf(i8* nocapture, i32, i8* nocapture readonly, ...) local_unnamed_addr #1 -attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #2 = { nounwind } + diff --git a/llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll b/llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll index f45058f..ab8b00d 100644 --- a/llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll +++ b/llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll @@ -82,7 +82,7 @@ declare i64 @llvm.hexagon.A2.addp(i64, i64) #1 declare i64 @llvm.hexagon.A2.subp(i64, i64) #1 declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1 -attributes #0 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } attributes #1 = { nounwind readnone } !0 = !{!1, !1, i64 0} diff --git a/llvm/test/CodeGen/Hexagon/early-if-vecpi.ll b/llvm/test/CodeGen/Hexagon/early-if-vecpi.ll index 6f3ec2d..6fd2aa1 100644 --- a/llvm/test/CodeGen/Hexagon/early-if-vecpi.ll +++ b/llvm/test/CodeGen/Hexagon/early-if-vecpi.ll @@ -66,4 +66,4 @@ for.end: ; preds = %if.end ret void } -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } diff --git a/llvm/test/CodeGen/Hexagon/early-if-vecpred.ll b/llvm/test/CodeGen/Hexagon/early-if-vecpred.ll index ca119e1..0507433 100644 --- a/llvm/test/CodeGen/Hexagon/early-if-vecpred.ll +++ b/llvm/test/CodeGen/Hexagon/early-if-vecpred.ll @@ -31,7 +31,7 @@ b5: ; preds = %b3, %b1 declare <1024 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32) #1 declare <1024 x i1> @llvm.hexagon.V6.pred.not.128B(<1024 x i1>) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll b/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll index b3a4a2f..4c93ab2 100644 --- a/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll +++ b/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll @@ -139,5 +139,5 @@ declare <64 x i32> @llvm.hexagon.V6.vmpyuh.acc.128B(<64 x i32>, <32 x i32>, i32) declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll b/llvm/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll index ce7f5e0..350b0ed 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll @@ -51,4 +51,4 @@ b23: ; preds = %b0 ret void } -attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll b/llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll index ecec836..dbcba1a 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll @@ -42,4 +42,4 @@ b20: ; preds = %b2 br label %b1 } -attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/expand-vselect-kill.ll b/llvm/test/CodeGen/Hexagon/expand-vselect-kill.ll index 1d07859..a5769db 100644 --- a/llvm/test/CodeGen/Hexagon/expand-vselect-kill.ll +++ b/llvm/test/CodeGen/Hexagon/expand-vselect-kill.ll @@ -48,6 +48,6 @@ declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #2 declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #2 declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #2 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } -attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } +attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } attributes #2 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef.ll b/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef.ll index 8524bf3..88eaec9 100644 --- a/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef.ll +++ b/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef.ll @@ -91,5 +91,5 @@ b22: ; preds = %b22, %b18 attributes #0 = { nounwind } attributes #1 = { nounwind readnone } -attributes #2 = { nounwind "reciprocal-estimates"="none" "target-cpu"="hexagonv60" "target-features"="+hvx-double" } +attributes #2 = { nounwind "reciprocal-estimates"="none" "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } attributes #3 = { nobuiltin nounwind } diff --git a/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll b/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll index 4f2bb86..641d53c 100644 --- a/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll +++ b/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll @@ -210,7 +210,7 @@ b34: ; preds = %b34, %b24 br i1 %v146, label %b33, label %b34 } -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } attributes #3 = { nobuiltin nounwind } diff --git a/llvm/test/CodeGen/Hexagon/find-loop-instr.ll b/llvm/test/CodeGen/Hexagon/find-loop-instr.ll index 1234baf..b9743ad 100644 --- a/llvm/test/CodeGen/Hexagon/find-loop-instr.ll +++ b/llvm/test/CodeGen/Hexagon/find-loop-instr.ll @@ -76,4 +76,4 @@ b21: ; preds = %b20, %b19, %b16, %b br i1 %v23, label %b13, label %b10 } -attributes #0 = { norecurse "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { norecurse "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/fminmax.ll b/llvm/test/CodeGen/Hexagon/fminmax.ll index 7c1a9fb..cf1dc6c 100644 --- a/llvm/test/CodeGen/Hexagon/fminmax.ll +++ b/llvm/test/CodeGen/Hexagon/fminmax.ll @@ -22,6 +22,6 @@ entry: declare float @fminf(float, float) #0 declare float @fmaxf(float, float) #0 -attributes #0 = { nounwind readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll b/llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll index 43d5fd5..88d4e28 100644 --- a/llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll +++ b/llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll @@ -156,7 +156,7 @@ declare <32 x i32> @llvm.hexagon.V6.vmpahb.acc(<32 x i32>, <32 x i32>, i32) #0 declare <32 x i32> @llvm.hexagon.V6.vmpyhsat.acc(<32 x i32>, <16 x i32>, i32) #0 attributes #0 = { nounwind readnone } -attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } !1 = !{!2, !2, i64 0} !2 = !{!"omnipotent char", !3, i64 0} diff --git a/llvm/test/CodeGen/Hexagon/hasfp-crash1.ll b/llvm/test/CodeGen/Hexagon/hasfp-crash1.ll index 1154a71..f96eafe 100644 --- a/llvm/test/CodeGen/Hexagon/hasfp-crash1.ll +++ b/llvm/test/CodeGen/Hexagon/hasfp-crash1.ll @@ -18,7 +18,7 @@ entry: ; Function Attrs: nounwind readnone speculatable declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 -attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx-double,-long-calls" } +attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx,-long-calls" } attributes #1 = { nounwind readnone speculatable } !llvm.dbg.cu = !{!0} diff --git a/llvm/test/CodeGen/Hexagon/hasfp-crash2.ll b/llvm/test/CodeGen/Hexagon/hasfp-crash2.ll index c8b4994..c454a9f 100644 --- a/llvm/test/CodeGen/Hexagon/hasfp-crash2.ll +++ b/llvm/test/CodeGen/Hexagon/hasfp-crash2.ll @@ -19,7 +19,7 @@ entry: ; Function Attrs: nounwind readnone speculatable declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 -attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx-double,-long-calls" } +attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"=",-hvx,-long-calls" } attributes #1 = { nounwind readnone speculatable } !llvm.dbg.cu = !{!0} diff --git a/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll b/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll index 1719003..ca1ba2f 100644 --- a/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll +++ b/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll @@ -73,7 +73,7 @@ declare <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32>, <32 x i32>) #1 ; Function Attrs: nounwind readnone declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #1 -attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll b/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll index 3808364..8fb62b3 100644 --- a/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll +++ b/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll @@ -73,7 +73,7 @@ declare <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32>, <32 x i32>) #1 ; Function Attrs: nounwind readnone declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #1 -attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/Hexagon/hvx-nontemporal.ll b/llvm/test/CodeGen/Hexagon/hvx-nontemporal.ll index 98c5ef4..38e597d 100644 --- a/llvm/test/CodeGen/Hexagon/hvx-nontemporal.ll +++ b/llvm/test/CodeGen/Hexagon/hvx-nontemporal.ll @@ -20,7 +20,7 @@ entry: ret void } -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } !1 = !{!2, !2, i64 0} !2 = !{!"omnipotent char", !3, i64 0} diff --git a/llvm/test/CodeGen/Hexagon/hwloop-noreturn-call.ll b/llvm/test/CodeGen/Hexagon/hwloop-noreturn-call.ll index 1045e2e..accf6fd 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-noreturn-call.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-noreturn-call.ll @@ -58,6 +58,6 @@ noret: declare void @trap() #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } attributes #1 = { nounwind noreturn } diff --git a/llvm/test/CodeGen/Hexagon/hwloop-preh.ll b/llvm/test/CodeGen/Hexagon/hwloop-preh.ll index e92461f..fb7e768 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-preh.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-preh.ll @@ -41,4 +41,4 @@ return: ; preds = %return.loopexit, %f !1 = !{!"omnipotent char", !2} !2 = !{!"Simple C/C++ TBAA"} -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx" } diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll b/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll index 2563421..d540c09 100644 --- a/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll +++ b/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll @@ -15,5 +15,5 @@ entry: ret void } -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-vecpred128.ll b/llvm/test/CodeGen/Hexagon/inline-asm-vecpred128.ll index 234f5a0..7d2f50e 100644 --- a/llvm/test/CodeGen/Hexagon/inline-asm-vecpred128.ll +++ b/llvm/test/CodeGen/Hexagon/inline-asm-vecpred128.ll @@ -12,4 +12,4 @@ define void @fred() #0 { ret void } -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/byte-store-double.ll b/llvm/test/CodeGen/Hexagon/intrinsics/byte-store-double.ll index 2a54bfe..3b853eb 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/byte-store-double.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/byte-store-double.ll @@ -1,4 +1,4 @@ -; RUN: llc -mattr=+hvx-double -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mattr=+hvxv60,hvx-length128b -march=hexagon -O2 < %s | FileCheck %s ; CHECK-LABEL: V6_vmaskedstoreq_128B ; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}} diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/byte-store.ll b/llvm/test/CodeGen/Hexagon/intrinsics/byte-store.ll index 208c15f..5ff6722 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/byte-store.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/byte-store.ll @@ -1,4 +1,4 @@ -; RUN: llc -mattr=+hvx -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mattr=+hvxv60,hvx-length64b -march=hexagon -O2 < %s | FileCheck %s ; CHECK-LABEL: V6_vmaskedstoreq ; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}} diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll b/llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll index 23473c9..1a5fd13 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll @@ -65,7 +65,7 @@ declare void @llvm.hexagon.Y2.dczeroa(i8* nocapture) #3 declare void @llvm.hexagon.Y4.l2fetch(i8* nocapture readonly, i32) #2 declare void @llvm.hexagon.Y5.l2fetch(i8* nocapture readonly, i64) #2 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } attributes #1 = { inaccessiblemem_or_argmemonly nounwind } attributes #2 = { nounwind } attributes #3 = { argmemonly nounwind writeonly } diff --git a/llvm/test/CodeGen/Hexagon/jt-in-text.ll b/llvm/test/CodeGen/Hexagon/jt-in-text.ll index 62b5cae..7389c960 100644 --- a/llvm/test/CodeGen/Hexagon/jt-in-text.ll +++ b/llvm/test/CodeGen/Hexagon/jt-in-text.ll @@ -54,4 +54,4 @@ sw.epilog: ; preds = %entry, %sw.bb4, %sw ret void } -attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll index f738282..92f3b60 100644 --- a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll +++ b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll @@ -80,4 +80,4 @@ if.end437: ; preds = %if.then409, %for.bo br label %for.body405 } -attributes #0 = { noinline nounwind "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" } +attributes #0 = { noinline nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll index 9907ae7..3e1e39b 100644 --- a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll +++ b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll @@ -81,4 +81,4 @@ b46: ; preds = %b3 ret i16 %v5 } -attributes #0 = { noinline nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { noinline nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/loop-prefetch.ll b/llvm/test/CodeGen/Hexagon/loop-prefetch.ll index 0c6e458..2451842 100644 --- a/llvm/test/CodeGen/Hexagon/loop-prefetch.ll +++ b/llvm/test/CodeGen/Hexagon/loop-prefetch.ll @@ -24,4 +24,4 @@ while.end: ; preds = %while.body, %entry ret void } -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx" } diff --git a/llvm/test/CodeGen/Hexagon/lower-extract-subvector.ll b/llvm/test/CodeGen/Hexagon/lower-extract-subvector.ll index ba67de9..09ca465 100644 --- a/llvm/test/CodeGen/Hexagon/lower-extract-subvector.ll +++ b/llvm/test/CodeGen/Hexagon/lower-extract-subvector.ll @@ -43,5 +43,5 @@ if.then.i164: ; preds = %"consume denoised" ; Function Attrs: nounwind readnone declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } -attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } +attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } diff --git a/llvm/test/CodeGen/Hexagon/memops-stack.ll b/llvm/test/CodeGen/Hexagon/memops-stack.ll index 1aa2e30..9da319f 100644 --- a/llvm/test/CodeGen/Hexagon/memops-stack.ll +++ b/llvm/test/CodeGen/Hexagon/memops-stack.ll @@ -136,9 +136,9 @@ declare void @foo(i32*) #2 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind } -attributes #2 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #3 = { nounwind } !1 = !{!2, !2, i64 0} diff --git a/llvm/test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll b/llvm/test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll index 25cb14e..c147282 100644 --- a/llvm/test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll +++ b/llvm/test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll @@ -42,6 +42,6 @@ entry: declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } -attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } +attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } diff --git a/llvm/test/CodeGen/Hexagon/multi-cycle.ll b/llvm/test/CodeGen/Hexagon/multi-cycle.ll index fc02182..b8caef9 100644 --- a/llvm/test/CodeGen/Hexagon/multi-cycle.ll +++ b/llvm/test/CodeGen/Hexagon/multi-cycle.ll @@ -95,7 +95,7 @@ declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #1 declare <16 x i32> @llvm.hexagon.V6.vabsdiffh(<16 x i32>, <16 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.vabsh(<16 x i32>) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #1 = { nounwind readnone } !1 = !{!2, !2, i64 0} diff --git a/llvm/test/CodeGen/Hexagon/newify-crash.ll b/llvm/test/CodeGen/Hexagon/newify-crash.ll index 705170b..bb29954 100644 --- a/llvm/test/CodeGen/Hexagon/newify-crash.ll +++ b/llvm/test/CodeGen/Hexagon/newify-crash.ll @@ -40,5 +40,5 @@ b18: ; preds = %b7 declare <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32>, <32 x i32>) #1 declare void @f0() #0 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/newvaluejump3.ll b/llvm/test/CodeGen/Hexagon/newvaluejump3.ll index 1e2e6c2..9347966 100644 --- a/llvm/test/CodeGen/Hexagon/newvaluejump3.ll +++ b/llvm/test/CodeGen/Hexagon/newvaluejump3.ll @@ -74,6 +74,6 @@ b24: ; preds = %b20, %b16, %b9, %b2 } attributes #0 = { argmemonly nounwind } -attributes #1 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double,-long-calls" } -attributes #2 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double,-long-calls" } +attributes #1 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b,-long-calls" } +attributes #2 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll b/llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll index 03de1532..4a24ea6 100644 --- a/llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll +++ b/llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll @@ -23,5 +23,5 @@ for.end13: ; preds = %for.cond ret void } -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } diff --git a/llvm/test/CodeGen/Hexagon/plt-rel.ll b/llvm/test/CodeGen/Hexagon/plt-rel.ll index 1d38cf3..d1d97a6 100644 --- a/llvm/test/CodeGen/Hexagon/plt-rel.ll +++ b/llvm/test/CodeGen/Hexagon/plt-rel.ll @@ -34,4 +34,4 @@ return: ; preds = %entry, %if.then ret i1 %.sink } -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } diff --git a/llvm/test/CodeGen/Hexagon/post-inc-aa-metadata.ll b/llvm/test/CodeGen/Hexagon/post-inc-aa-metadata.ll index fb2f038..673a9b4 100644 --- a/llvm/test/CodeGen/Hexagon/post-inc-aa-metadata.ll +++ b/llvm/test/CodeGen/Hexagon/post-inc-aa-metadata.ll @@ -29,7 +29,7 @@ while.end: ; preds = %while.body, %entry ret void } -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } !1 = !{!2, !2, i64 0} diff --git a/llvm/test/CodeGen/Hexagon/propagate-vcombine.ll b/llvm/test/CodeGen/Hexagon/propagate-vcombine.ll index 4948a89..989322a 100644 --- a/llvm/test/CodeGen/Hexagon/propagate-vcombine.ll +++ b/llvm/test/CodeGen/Hexagon/propagate-vcombine.ll @@ -42,7 +42,7 @@ declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #3 declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #3 declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #3 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } -attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } -attributes #2 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx" } -attributes #3 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } +attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } +attributes #2 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } +attributes #3 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } diff --git a/llvm/test/CodeGen/Hexagon/rdf-def-mask.ll b/llvm/test/CodeGen/Hexagon/rdf-def-mask.ll index 3d65968..91aec77 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-def-mask.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-def-mask.ll @@ -48,5 +48,5 @@ declare i32 @llvm.hexagon.S2.clb(i32) #1 declare i32 @llvm.hexagon.S2.asl.r.r(i32, i32) #1 declare i32 @llvm.hexagon.M2.mpyu.nac.ll.s0(i32, i32, i32) #1 -attributes #0 = { nounwind readnone "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind readnone "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll b/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll index 222d8a2..d06da93 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll @@ -26,7 +26,7 @@ declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 ; Function Attrs: argmemonly nounwind declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll b/llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll index ae090626..2661f8c 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll @@ -24,7 +24,7 @@ if.end: ; preds = %if.then, %entry ret i32 %retval1.0 } -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind } !1 = !{i32 155} diff --git a/llvm/test/CodeGen/Hexagon/reg-scavengebug-3.ll b/llvm/test/CodeGen/Hexagon/reg-scavengebug-3.ll index db9ed55..c73d4c7 100644 --- a/llvm/test/CodeGen/Hexagon/reg-scavengebug-3.ll +++ b/llvm/test/CodeGen/Hexagon/reg-scavengebug-3.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -march=hexagon -mcpu=hexagonv60 < %s | FileCheck %s +; RUN: llc -O0 -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s ; CHECK: vmem diff --git a/llvm/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll b/llvm/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll index 78c4b98..bc878e0 100644 --- a/llvm/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll +++ b/llvm/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll @@ -95,6 +95,6 @@ entry: ret void } -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir b/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir index a541e76..7e18011 100644 --- a/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir +++ b/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir @@ -58,7 +58,7 @@ declare i32 @lrand48() #0 declare i64 @llvm.hexagon.S2.extractup(i64, i32, i32) #1 - attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double" } + attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx" } attributes #1 = { nounwind readnone } ... diff --git a/llvm/test/CodeGen/Hexagon/regalloc-block-overlap.ll b/llvm/test/CodeGen/Hexagon/regalloc-block-overlap.ll index c98fcb6..2dc9a7a 100644 --- a/llvm/test/CodeGen/Hexagon/regalloc-block-overlap.ll +++ b/llvm/test/CodeGen/Hexagon/regalloc-block-overlap.ll @@ -138,6 +138,6 @@ b42: ; preds = %b40 br label %b39 } -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/Hexagon/select-instr-align.ll b/llvm/test/CodeGen/Hexagon/select-instr-align.ll index e3b2929..368ee3c 100644 --- a/llvm/test/CodeGen/Hexagon/select-instr-align.ll +++ b/llvm/test/CodeGen/Hexagon/select-instr-align.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-hexagon-hvx < %s | FileCheck %s +; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s ; CHECK-LABEL: aligned_load: ; CHECK: = vmem({{.*}}) ; CHECK-LABEL: aligned_store: diff --git a/llvm/test/CodeGen/Hexagon/stack-align-reset.ll b/llvm/test/CodeGen/Hexagon/stack-align-reset.ll index 0d028fb..f7639c7 100644 --- a/llvm/test/CodeGen/Hexagon/stack-align-reset.ll +++ b/llvm/test/CodeGen/Hexagon/stack-align-reset.ll @@ -47,5 +47,5 @@ b11: ; preds = %b11, %b7 declare i32 @llvm.hexagon.V6.extractw(<16 x i32>, i32) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/store-shift.ll b/llvm/test/CodeGen/Hexagon/store-shift.ll index 981071a..f7bed98 100644 --- a/llvm/test/CodeGen/Hexagon/store-shift.ll +++ b/llvm/test/CodeGen/Hexagon/store-shift.ll @@ -42,7 +42,7 @@ entry: ret void } -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } !1 = !{!2, !2, i64 0} !2 = !{!"int", !3, i64 0} diff --git a/llvm/test/CodeGen/Hexagon/switch-lut-explicit-section.ll b/llvm/test/CodeGen/Hexagon/switch-lut-explicit-section.ll index 6c67a0d..b80e8e3 100644 --- a/llvm/test/CodeGen/Hexagon/switch-lut-explicit-section.ll +++ b/llvm/test/CodeGen/Hexagon/switch-lut-explicit-section.ll @@ -29,4 +29,4 @@ return: ; preds = %entry ret i32 19 } -attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Hexagon/switch-lut-function-section.ll b/llvm/test/CodeGen/Hexagon/switch-lut-function-section.ll index bb2b1e7..542bfbb 100644 --- a/llvm/test/CodeGen/Hexagon/switch-lut-function-section.ll +++ b/llvm/test/CodeGen/Hexagon/switch-lut-function-section.ll @@ -27,4 +27,4 @@ return: ; preds = %entry ret i32 19 } -attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Hexagon/switch-lut-multiple-functions.ll b/llvm/test/CodeGen/Hexagon/switch-lut-multiple-functions.ll index 57fdfbf..22b61f0 100644 --- a/llvm/test/CodeGen/Hexagon/switch-lut-multiple-functions.ll +++ b/llvm/test/CodeGen/Hexagon/switch-lut-multiple-functions.ll @@ -39,4 +39,4 @@ return: ; preds = %entry ret i32 19 } -attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Hexagon/switch-lut-text-section.ll b/llvm/test/CodeGen/Hexagon/switch-lut-text-section.ll index b4d3e89..203ea4a 100644 --- a/llvm/test/CodeGen/Hexagon/switch-lut-text-section.ll +++ b/llvm/test/CodeGen/Hexagon/switch-lut-text-section.ll @@ -24,4 +24,4 @@ return: ; preds = %entry ret i32 19 } -attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Hexagon/undo-dag-shift.ll b/llvm/test/CodeGen/Hexagon/undo-dag-shift.ll index c1ab5d7..5aa7f39 100644 --- a/llvm/test/CodeGen/Hexagon/undo-dag-shift.ll +++ b/llvm/test/CodeGen/Hexagon/undo-dag-shift.ll @@ -54,6 +54,6 @@ entry: ret void } -attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } -attributes #1 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } +attributes #1 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/v60-cur.ll b/llvm/test/CodeGen/Hexagon/v60-cur.ll index a7d4f6d..26d40c9 100644 --- a/llvm/test/CodeGen/Hexagon/v60-cur.ll +++ b/llvm/test/CodeGen/Hexagon/v60-cur.ll @@ -54,7 +54,7 @@ declare <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32>, <16 x i32>, i32) #1 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #1 = { nounwind readnone } !1 = !{!2, !2, i64 0} diff --git a/llvm/test/CodeGen/Hexagon/v60-vsel1.ll b/llvm/test/CodeGen/Hexagon/v60-vsel1.ll index e673145..71d112c 100644 --- a/llvm/test/CodeGen/Hexagon/v60-vsel1.ll +++ b/llvm/test/CodeGen/Hexagon/v60-vsel1.ll @@ -65,5 +65,5 @@ declare <16 x i32> @llvm.hexagon.V6.vandqrt(<512 x i1>, i32) #1 declare <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.vand(<16 x i32>, <16 x i32>) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/v60Intrins.ll b/llvm/test/CodeGen/Hexagon/v60Intrins.ll index d0064c5..980d870 100644 --- a/llvm/test/CodeGen/Hexagon/v60Intrins.ll +++ b/llvm/test/CodeGen/Hexagon/v60Intrins.ll @@ -2555,5 +2555,5 @@ declare <32 x i32> @llvm.hexagon.V6.vunpackh(<16 x i32>) #1 ; Function Attrs: nounwind readnone declare <32 x i32> @llvm.hexagon.V6.vunpackoh(<32 x i32>, <16 x i32>) #1 -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/v60Vasr.ll b/llvm/test/CodeGen/Hexagon/v60Vasr.ll index fb177f6..dd309f6 100644 --- a/llvm/test/CodeGen/Hexagon/v60Vasr.ll +++ b/llvm/test/CodeGen/Hexagon/v60Vasr.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -mcpu=hexagonv60 < %s | FileCheck %s +; RUN: llc -march=hexagon -O2 -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s ; CHECK: vasr(v{{[0-9]+}}.h,v{{[0-9]+}}.h,r{{[0-7]+}}):sat diff --git a/llvm/test/CodeGen/Hexagon/v60small.ll b/llvm/test/CodeGen/Hexagon/v60small.ll index 8a6a615..efa726e 100644 --- a/llvm/test/CodeGen/Hexagon/v60small.ll +++ b/llvm/test/CodeGen/Hexagon/v60small.ll @@ -47,5 +47,5 @@ declare <512 x i1> @llvm.hexagon.V6.pred.and(<512 x i1>, <512 x i1>) #1 ; Function Attrs: nounwind readnone declare <512 x i1> @llvm.hexagon.V6.pred.and.n(<512 x i1>, <512 x i1>) #1 -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll b/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll index 24daeac..18c2cf6 100644 --- a/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll +++ b/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck %s -; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s +; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck --check-prefix=CHECK %s +; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s ; generate .long XXXX which is a vector debug print instruction. ; CHECK: .long 0x1dffe0 ; CHECK: .long 0x1dffe0 diff --git a/llvm/test/CodeGen/Hexagon/vassign-to-combine.ll b/llvm/test/CodeGen/Hexagon/vassign-to-combine.ll index a9a0d51..0facdc3 100644 --- a/llvm/test/CodeGen/Hexagon/vassign-to-combine.ll +++ b/llvm/test/CodeGen/Hexagon/vassign-to-combine.ll @@ -52,5 +52,5 @@ b2: ; preds = %b1 } attributes #0 = { nounwind readnone } -attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } diff --git a/llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll b/llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll index 7e41bd4..352398e 100644 --- a/llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll +++ b/llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll @@ -155,8 +155,8 @@ destructor_block: ; preds = %"for testOne.s0.x.x ; Function Attrs: nounwind readnone declare <16 x i32> @llvm.hexagon.V6.vdmpyhvsat(<16 x i32>, <16 x i32>) #1 -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } -attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } +attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } !5 = !{!6, !6, i64 0} !6 = !{!"inputOne", !7} diff --git a/llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll b/llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll index d120295..40b4a819 100644 --- a/llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll +++ b/llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2 -enable-hexagon-hvx < %s | FileCheck %s +; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s ; CHECK: vmem(r{{[0-9]+}}+#3) = v{{[0-9]+}} ; CHECK: call puts diff --git a/llvm/test/CodeGen/Hexagon/vec-vararg-align.ll b/llvm/test/CodeGen/Hexagon/vec-vararg-align.ll index d4c6bd3..0101c1f 100644 --- a/llvm/test/CodeGen/Hexagon/vec-vararg-align.ll +++ b/llvm/test/CodeGen/Hexagon/vec-vararg-align.ll @@ -27,4 +27,4 @@ b0: declare i32 @printf(i8*, ...) #0 declare void @VarVec1(i8*, i32, ...) #0 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } diff --git a/llvm/test/CodeGen/Hexagon/vector-align.ll b/llvm/test/CodeGen/Hexagon/vector-align.ll index 557ee3f..043839c 100644 --- a/llvm/test/CodeGen/Hexagon/vector-align.ll +++ b/llvm/test/CodeGen/Hexagon/vector-align.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx < %s \ +; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s \ ; RUN: | FileCheck %s ; Check that the store to Q6VecPredResult does not get expanded into multiple diff --git a/llvm/test/CodeGen/Hexagon/vload-postinc-sel.ll b/llvm/test/CodeGen/Hexagon/vload-postinc-sel.ll index 70ed3a9b1..a3bed31 100644 --- a/llvm/test/CodeGen/Hexagon/vload-postinc-sel.ll +++ b/llvm/test/CodeGen/Hexagon/vload-postinc-sel.ll @@ -49,4 +49,4 @@ call_destructor.exit: ; preds = %entry declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #0 attributes #0 = { nounwind readnone } -attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } diff --git a/llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll b/llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll index 9c35990..8b207ba 100644 --- a/llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll +++ b/llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll @@ -133,8 +133,8 @@ destructor_block: ; preds = %"for testOne.s0.x.x ; Function Attrs: nounwind readnone declare <32 x i32> @llvm.hexagon.V6.vmpabuuv(<32 x i32>, <32 x i32>) #1 -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } -attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } +attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } !5 = !{!6, !6, i64 0} !6 = !{!"inputOne", !7} diff --git a/llvm/test/CodeGen/Hexagon/vpack_eo.ll b/llvm/test/CodeGen/Hexagon/vpack_eo.ll index 7238ca8..cf8619c 100644 --- a/llvm/test/CodeGen/Hexagon/vpack_eo.ll +++ b/llvm/test/CodeGen/Hexagon/vpack_eo.ll @@ -61,8 +61,8 @@ entry: ; Function Attrs: nounwind readnone declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1 -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } -attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } +attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } !4 = !{!5, !5, i64 0} !5 = !{!"InputOne", !6} diff --git a/llvm/test/CodeGen/Hexagon/vselect-pseudo.ll b/llvm/test/CodeGen/Hexagon/vselect-pseudo.ll index ef86e47..e6be3ee 100644 --- a/llvm/test/CodeGen/Hexagon/vselect-pseudo.ll +++ b/llvm/test/CodeGen/Hexagon/vselect-pseudo.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -march=hexagon -mattr="+hvxv60,+hvx-length64b" < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/MC/Hexagon/align.s b/llvm/test/MC/Hexagon/align.s index 80cebf1..e85534d 100644 --- a/llvm/test/MC/Hexagon/align.s +++ b/llvm/test/MC/Hexagon/align.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s +# RUN: llvm-mc -triple=hexagon -filetype=obj -mhvx %s | llvm-objdump -mhvx -d - | FileCheck %s # Verify that the .align directive emits the proper insn packets. diff --git a/llvm/test/MC/Hexagon/double-vector-producer.s b/llvm/test/MC/Hexagon/double-vector-producer.s index 5421653..e10917b 100644 --- a/llvm/test/MC/Hexagon/double-vector-producer.s +++ b/llvm/test/MC/Hexagon/double-vector-producer.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -filetype=obj %s | llvm-objdump -d - | FileCheck %s +# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mhvx -filetype=obj %s | llvm-objdump -d - | FileCheck %s { v1:0 = vshuff(v1,v0,r7) v2.w = vadd(v13.w,v15.w) diff --git a/llvm/test/MC/Hexagon/test.s b/llvm/test/MC/Hexagon/test.s index 73b6d0a..35a395a 100644 --- a/llvm/test/MC/Hexagon/test.s +++ b/llvm/test/MC/Hexagon/test.s @@ -1,4 +1,4 @@ -#RUN: llvm-mc -filetype=obj -triple=hexagon -mcpu=hexagonv60 %s +#RUN: llvm-mc -filetype=obj -triple=hexagon -mcpu=hexagonv60 -mhvx %s { vmem (r0 + #0) = v0 - r0 = memw(r0) } \ No newline at end of file + r0 = memw(r0) } diff --git a/llvm/test/MC/Hexagon/v60-alu.s b/llvm/test/MC/Hexagon/v60-alu.s index 1583c3d..856a9fe 100644 --- a/llvm/test/MC/Hexagon/v60-alu.s +++ b/llvm/test/MC/Hexagon/v60-alu.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s #CHECK: 1ce2cbd7 { v23.w = vavg(v11.w,{{ *}}v2.w):rnd } diff --git a/llvm/test/MC/Hexagon/v60-misc.s b/llvm/test/MC/Hexagon/v60-misc.s index b278447..53872d6 100644 --- a/llvm/test/MC/Hexagon/v60-misc.s +++ b/llvm/test/MC/Hexagon/v60-misc.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mattr=+hvx -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv60 -d - | FileCheck %s +# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mattr=+hvx -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv60 -mhvx -d - | FileCheck %s .L0: diff --git a/llvm/test/MC/Hexagon/v60-permute.s b/llvm/test/MC/Hexagon/v60-permute.s index b3544bd..0b0697a 100644 --- a/llvm/test/MC/Hexagon/v60-permute.s +++ b/llvm/test/MC/Hexagon/v60-permute.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s #CHECK: 1fd2d5cf { v15.b = vpack(v21.h{{ *}},{{ *}}v18.h):sat } diff --git a/llvm/test/MC/Hexagon/v60-shift.s b/llvm/test/MC/Hexagon/v60-shift.s index 3d0c334..0002714 100644 --- a/llvm/test/MC/Hexagon/v60-shift.s +++ b/llvm/test/MC/Hexagon/v60-shift.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s #CHECK: 198fd829 { v9.uw = vlsr(v24.uw,{{ *}}r15) } diff --git a/llvm/test/MC/Hexagon/v60-vcmp.s b/llvm/test/MC/Hexagon/v60-vcmp.s index c7f4e12..712f570 100644 --- a/llvm/test/MC/Hexagon/v60-vcmp.s +++ b/llvm/test/MC/Hexagon/v60-vcmp.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s #CHECK: 1c81f142 { q2 |= vcmp.eq(v17.b{{ *}},{{ *}}v1.b) } diff --git a/llvm/test/MC/Hexagon/v60-vmem.s b/llvm/test/MC/Hexagon/v60-vmem.s index 0580a1e..bf549c8 100644 --- a/llvm/test/MC/Hexagon/v60-vmem.s +++ b/llvm/test/MC/Hexagon/v60-vmem.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s #CHECK: 292cc11b { vmem(r12++#1) = v27 } diff --git a/llvm/test/MC/Hexagon/v60-vmpy-acc.s b/llvm/test/MC/Hexagon/v60-vmpy-acc.s index c39a925..a582a5f 100644 --- a/llvm/test/MC/Hexagon/v60-vmpy-acc.s +++ b/llvm/test/MC/Hexagon/v60-vmpy-acc.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s #CHECK: 1936ee37 { v23.w += vdmpy(v15:14.h,r22.uh,#1):sat } diff --git a/llvm/test/MC/Hexagon/v60-vmpy1.s b/llvm/test/MC/Hexagon/v60-vmpy1.s index 1f36a5e..dd86a08 100644 --- a/llvm/test/MC/Hexagon/v60-vmpy1.s +++ b/llvm/test/MC/Hexagon/v60-vmpy1.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s #CHECK: 1939c223 { v3.w = vdmpy(v3:2.h,{{ *}}r25.uh,{{ *}}#1):sat } diff --git a/llvm/test/MC/Hexagon/v60lookup.s b/llvm/test/MC/Hexagon/v60lookup.s index b92a2d3..d4c5202 100644 --- a/llvm/test/MC/Hexagon/v60lookup.s +++ b/llvm/test/MC/Hexagon/v60lookup.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s V31.b = vlut32(V29.b, V15.b, R1) diff --git a/llvm/test/MC/Hexagon/v62_all.s b/llvm/test/MC/Hexagon/v62_all.s index 6effdc0..79e3098 100644 --- a/llvm/test/MC/Hexagon/v62_all.s +++ b/llvm/test/MC/Hexagon/v62_all.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv62 -d - | FileCheck %s +# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj -mhvx %s | llvm-objdump -arch=hexagon -mcpu=hexagonv62 -mhvx -d - | FileCheck %s // V6_lvsplatb // Vd32.b=vsplat(Rt32) diff --git a/llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll b/llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll index 4bc1251..a81737a 100644 --- a/llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll +++ b/llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll @@ -59,4 +59,4 @@ return: ; preds = %sw.default, %sw.bb5 ret i32 %1 } -attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/tools/llvm-objdump/Hexagon/source-interleave-hexagon.ll b/llvm/test/tools/llvm-objdump/Hexagon/source-interleave-hexagon.ll index b14eb2a..fd35372 100644 --- a/llvm/test/tools/llvm-objdump/Hexagon/source-interleave-hexagon.ll +++ b/llvm/test/tools/llvm-objdump/Hexagon/source-interleave-hexagon.ll @@ -34,7 +34,7 @@ entry: ; Function Attrs: nounwind readnone declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } !llvm.dbg.cu = !{!0}