From: Changbin Du Date: Wed, 8 May 2019 15:21:41 +0000 (+0800) Subject: Documentation: x86: convert x86_64/machinecheck to reST X-Git-Tag: v5.15~6391^2^2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e115fb4bd2667754135d0436b6419fb171e9ea4a;p=platform%2Fkernel%2Flinux-starfive.git Documentation: x86: convert x86_64/machinecheck to reST This converts the plain text documentation to reStructuredText format and add it to Sphinx TOC tree. No essential content change. Signed-off-by: Changbin Du Reviewed-by: Mauro Carvalho Chehab Signed-off-by: Jonathan Corbet --- diff --git a/Documentation/x86/x86_64/index.rst b/Documentation/x86/x86_64/index.rst index c04b6eab..d6eaaa5 100644 --- a/Documentation/x86/x86_64/index.rst +++ b/Documentation/x86/x86_64/index.rst @@ -13,3 +13,4 @@ x86_64 Support 5level-paging fake-numa-for-cpusets cpu-hotplug-spec + machinecheck diff --git a/Documentation/x86/x86_64/machinecheck b/Documentation/x86/x86_64/machinecheck.rst similarity index 92% rename from Documentation/x86/x86_64/machinecheck rename to Documentation/x86/x86_64/machinecheck.rst index d0648a7..e189168 100644 --- a/Documentation/x86/x86_64/machinecheck +++ b/Documentation/x86/x86_64/machinecheck.rst @@ -1,5 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0 -Configurable sysfs parameters for the x86-64 machine check code. +=============================================================== +Configurable sysfs parameters for the x86-64 machine check code +=============================================================== Machine checks report internal hardware error conditions detected by the CPU. Uncorrected errors typically cause a machine check @@ -16,14 +19,13 @@ log then mcelog should run to collect and decode machine check entries from /dev/mcelog. Normally mcelog should be run regularly from a cronjob. Each CPU has a directory in /sys/devices/system/machinecheck/machinecheckN -(N = CPU number) +(N = CPU number). The directory contains some configurable entries: -Entries: - bankNctl -(N bank number) + (N bank number) + 64bit Hex bitmask enabling/disabling specific subevents for bank N When a bit in the bitmask is zero then the respective subevent will not be reported.