From: jeff <jrbyrnes1989@gmail.com>
Date: Wed, 3 Aug 2022 21:53:02 +0000 (-0700)
Subject: [AMDGPU] Precommit test case for D130729
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e0b16aaaf99784efbb9dd9624787554d5584701a;p=platform%2Fupstream%2Fllvm.git

[AMDGPU] Precommit test case for D130729

Change-Id: I23396655880b5732ad991d47e51900408f5bc5ee
---

diff --git a/llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll b/llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
new file mode 100644
index 0000000..4e1e303
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
@@ -0,0 +1,30 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=amdgcn -mcpu=gfx90a -O3 < %s | FileCheck %s
+
+declare double @llvm.amdgcn.flat.atomic.fadd.f64.p0f64.f64(double* nocapture, double) #8
+
+define protected amdgpu_kernel void @IllegalGEPConst(i32 %a, double addrspace(1)* %b, double %c) {
+; CHECK-LABEL: IllegalGEPConst:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    s_load_dword s2, s[0:1], 0x24
+; CHECK-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
+; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:    s_ashr_i32 s3, s2, 31
+; CHECK-NEXT:    s_lshl_b64 s[0:1], s[2:3], 3
+; CHECK-NEXT:    s_add_u32 s0, s4, s0
+; CHECK-NEXT:    s_addc_u32 s1, s5, s1
+; CHECK-NEXT:    v_mov_b32_e32 v0, s6
+; CHECK-NEXT:    v_mov_b32_e32 v1, s7
+; CHECK-NEXT:    v_pk_mov_b32 v[2:3], s[0:1], s[0:1] op_sel:[0,1]
+; CHECK-NEXT:    flat_atomic_add_f64 v[2:3], v[0:1] offset:65528
+; CHECK-NEXT:    s_endpgm
+entry:
+  %i = add nsw i32 %a, -1
+  %i.2 = sext i32 %i to i64
+  %i.3 = getelementptr inbounds double, double addrspace(1)* %b, i64 %i.2
+  %i.4 = addrspacecast double addrspace(1)* %i.3 to double*
+  %i.5 = tail call contract double @llvm.amdgcn.flat.atomic.fadd.f64.p0f64.f64(double* %i.4, double %c) #8
+  ret void
+}
+
+attributes #8 = { argmemonly mustprogress nounwind willreturn "target-cpu"="gfx90a" }