From: Chunming Zhou <David1.Zhou@amd.com>
Date: Thu, 8 Dec 2016 02:16:00 +0000 (+0800)
Subject: drm/amdgpu/soc15: add Raven golden setting
X-Git-Tag: v4.13-rc1~45^2~24^2~261
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e0ab9578685038ac5110b822b6628d4b6748ab13;p=platform%2Fkernel%2Flinux-exynos.git

drm/amdgpu/soc15: add Raven golden setting

Add the common golden settings for Raven.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 821b52f..a9ea060 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -206,6 +206,10 @@ static const u32 vega10_golden_init[] =
 {
 };
 
+static const u32 raven_golden_init[] =
+{
+};
+
 static void soc15_init_golden_registers(struct amdgpu_device *adev)
 {
 	/* Some of the registers might be dependent on GRBM_GFX_INDEX */
@@ -217,6 +221,11 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev)
 						 vega10_golden_init,
 						 (const u32)ARRAY_SIZE(vega10_golden_init));
 		break;
+	case CHIP_RAVEN:
+		amdgpu_program_register_sequence(adev,
+						 raven_golden_init,
+						 (const u32)ARRAY_SIZE(raven_golden_init));
+		break;
 	default:
 		break;
 	}