From: Florian Hahn <flo@fhahn.com>
Date: Sat, 12 Jun 2021 10:27:33 +0000 (+0100)
Subject: Revert "[X86FixupLEAs] Sub register usage of LEA dest should block LEA/SUB optimization"
X-Git-Tag: llvmorg-14-init~4142
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e087b4f14986f8330336b005c6ebb41f2bdaea63;p=platform%2Fupstream%2Fllvm.git

Revert "[X86FixupLEAs] Sub register usage of LEA dest should block LEA/SUB optimization"

This reverts commit f35bcea1d4748889b8240defdf00cb7a71cbe070 because it
depends on 1b748faf2bae246e2fc77d88420df13c2e60f4df, which breaks
building the llvm-test-suite with -verify-machineinstrs on X86.

See 154adc0f135cff3f8a8861c335d2b88c8049d098 for more details.
---

diff --git a/llvm/lib/Target/X86/X86FixupLEAs.cpp b/llvm/lib/Target/X86/X86FixupLEAs.cpp
index 12724f8..7a24129 100644
--- a/llvm/lib/Target/X86/X86FixupLEAs.cpp
+++ b/llvm/lib/Target/X86/X86FixupLEAs.cpp
@@ -418,30 +418,26 @@ FixupLEAPass::searchALUInst(MachineBasicBlock::iterator &I,
     // Check if the lea dest register is used in an add/sub instruction only.
     for (unsigned I = 0, E = CurInst->getNumOperands(); I != E; ++I) {
       MachineOperand &Opnd = CurInst->getOperand(I);
-      if (Opnd.isReg()) {
-        if (Opnd.getReg() == DestReg) {
-          if (Opnd.isDef() || !Opnd.isKill())
-            return MachineBasicBlock::iterator();
-
-          unsigned AluOpcode = CurInst->getOpcode();
-          if (AluOpcode != AddOpcode && AluOpcode != SubOpcode)
-            return MachineBasicBlock::iterator();
-
-          MachineOperand &Opnd2 = CurInst->getOperand(3 - I);
-          MachineOperand AluDest = CurInst->getOperand(0);
-          if (Opnd2.getReg() != AluDest.getReg())
-            return MachineBasicBlock::iterator();
-
-          // X - (Y + Z) may generate different flags than (X - Y) - Z when
-          // there is overflow. So we can't change the alu instruction if the
-          // flags register is live.
-          if (!CurInst->registerDefIsDead(X86::EFLAGS, TRI))
-            return MachineBasicBlock::iterator();
-
-          return CurInst;
-        }
-        if (TRI->regsOverlap(DestReg, Opnd.getReg()))
+      if (Opnd.isReg() && Opnd.getReg() == DestReg) {
+        if (Opnd.isDef() || !Opnd.isKill())
           return MachineBasicBlock::iterator();
+
+        unsigned AluOpcode = CurInst->getOpcode();
+        if (AluOpcode != AddOpcode && AluOpcode != SubOpcode)
+          return MachineBasicBlock::iterator();
+
+        MachineOperand &Opnd2 = CurInst->getOperand(3 - I);
+        MachineOperand AluDest = CurInst->getOperand(0);
+        if (Opnd2.getReg() != AluDest.getReg())
+          return MachineBasicBlock::iterator();
+
+        // X - (Y + Z) may generate different flags than (X - Y) - Z when there
+        // is overflow. So we can't change the alu instruction if the flags
+        // register is live.
+        if (!CurInst->registerDefIsDead(X86::EFLAGS, TRI))
+          return MachineBasicBlock::iterator();
+
+        return CurInst;
       }
     }
 
diff --git a/llvm/test/CodeGen/X86/lea-opt2.ll b/llvm/test/CodeGen/X86/lea-opt2.ll
index 5543602..e036a3f 100644
--- a/llvm/test/CodeGen/X86/lea-opt2.ll
+++ b/llvm/test/CodeGen/X86/lea-opt2.ll
@@ -182,32 +182,3 @@ endif:
   %sub1 = sub i64 %ld, %b
   ret i64 %sub1
 }
-
-; PR50615
-; The sub register usage of lea dest should block the transformation.
-define void @test9(i64 %p, i64 %s) {
-; CHECK-LABEL: test9:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    leaq (%rsi,%rdi), %rax
-; CHECK-NEXT:    xorl %ecx, %ecx
-; CHECK-NEXT:    testl $4095, %eax # imm = 0xFFF
-; CHECK-NEXT:    setne %cl
-; CHECK-NEXT:    shlq $12, %rcx
-; CHECK-NEXT:    addq %rax, %rcx
-; CHECK-NEXT:    andq $-4096, %rcx # imm = 0xF000
-; CHECK-NEXT:    addq %rcx, %rdi
-; CHECK-NEXT:    jmp bar@PLT # TAILCALL
-entry:
-  %add = add i64 %s, %p
-  %rem = and i64 %add, 4095
-  %cmp.not = icmp eq i64 %rem, 0
-  %add18 = select i1 %cmp.not, i64 0, i64 4096
-  %div9 = add i64 %add18, %add
-  %mul = and i64 %div9, -4096
-  %add2 = add i64 %mul, %p
-  tail call void @bar(i64 %add2, i64 %s)
-  ret void
-}
-
-declare void @bar(i64, i64)
-