From: Ivan Date: Wed, 22 Mar 2017 15:53:21 +0000 (+0900) Subject: s5j/watchdog: added low level code for WD maintenance X-Git-Tag: 1.1_Public_Release~614^2~257 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e081b9c7c1d624d3094c37537e5bcb5261021d9f;p=rtos%2Ftinyara.git s5j/watchdog: added low level code for WD maintenance This is low level chip dependent code to set configure basics features. More complex code, based on this code, should be located in board related directory. Change-Id: I441c156bbad625e9ffe532b666c09edf710efd7b Signed-off-by: Ivan --- diff --git a/os/arch/arm/include/s5j/s5j_watchdog.h b/os/arch/arm/include/s5j/s5j_watchdog.h new file mode 100644 index 0000000..902cae2 --- /dev/null +++ b/os/arch/arm/include/s5j/s5j_watchdog.h @@ -0,0 +1,98 @@ +/**************************************************************************** + * + * Copyright 2017 Samsung Electronics All Rights Reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * either express or implied. See the License for the specific + * language governing permissions and limitations under the License. + * + ****************************************************************************/ +/**************************************************************************** + * arch/arm/include/s5j/s5j_watchdog.h + * + * Copyright (C) 2009, 2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INC_S5J_S5J_WATCHDOG_H +#define __ARCH_ARM_INC_S5J_S5J_WATCHDOG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ +void s5j_watchdog_disable(void); + +#ifdef CONFIG_S5J_WATCHDOG +void s5j_watchdog_enable(void); +void s5j_watchdog_reset_disable(void); +void s5j_watchdog_reset_enable(void); +void s5j_watchdog_irq_disable(void); +void s5j_watchdog_irq_enable(void); +void s5j_watchdog_clk_set(unsigned int prescaler, unsigned int divider); +void s5j_watchdog_set_reload_val(unsigned int reload_val); +unsigned int s5j_watchdog_get_curr(void); +void s5j_watchdog_set_curr(unsigned int curr_val); +void s5j_watchdog_clear_int(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_INC_S5J_S5J_WATCHDOG_H */ diff --git a/os/arch/arm/src/s5j/Make.defs b/os/arch/arm/src/s5j/Make.defs index 569a350..0504ca4 100644 --- a/os/arch/arm/src/s5j/Make.defs +++ b/os/arch/arm/src/s5j/Make.defs @@ -211,6 +211,8 @@ ifeq ($(CONFIG_S5J_DMA),y) CHIP_CSRCS += s5j_dma.c endif +CHIP_CSRCS += s5j_watchdog.c + ifeq ($(CONFIG_S5J_SSS),y) EXTRA_LIBS += chip/soc/sss/libispdriver.a endif diff --git a/os/arch/arm/src/s5j/s5j_boot.c b/os/arch/arm/src/s5j/s5j_boot.c index 012704e..f7286ae 100644 --- a/os/arch/arm/src/s5j/s5j_boot.c +++ b/os/arch/arm/src/s5j/s5j_boot.c @@ -67,6 +67,7 @@ #include #include +#include #include "arm.h" #ifdef CONFIG_ARMV7M_MPU #include "mpu.h" @@ -88,21 +89,6 @@ extern uint32_t _vector_start; extern uint32_t _vector_end; -/**************************************************************************** - * Name: s5j_watchdog_disable - * - * Description: - * Disable the watchdog timer. The S5J always boots with the watchdog - * timer enabled at timeout of 10 - 20 seconds by the second stage boot - * loader to detect any boot failure. So, the watchdog timer must be - * disabled as part of the start up logic. - * - ****************************************************************************/ -static inline void s5j_watchdog_disable(void) -{ - unsigned int wtcon = getreg32(0x80030000) & ~(1 << 5); - putreg32(wtcon, 0x80030000); -} /**************************************************************************** * Public Functions diff --git a/os/arch/arm/src/s5j/s5j_watchdog.c b/os/arch/arm/src/s5j/s5j_watchdog.c new file mode 100644 index 0000000..34fbc6b --- /dev/null +++ b/os/arch/arm/src/s5j/s5j_watchdog.c @@ -0,0 +1,286 @@ +/**************************************************************************** + * + * Copyright 2016 Samsung Electronics All Rights Reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * either express or implied. See the License for the specific + * language governing permissions and limitations under the License. + * + ****************************************************************************/ +/**************************************************************************** + * arch/arm/src/s5j/s5j_watchdog.c + * + * Copyright (C) 2014-2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * The Samsung sample code has a BSD compatible license that requires this + * copyright notice: + * + * Copyright (c) 2016 Samsung Electronics, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ +#include +#include +#include +#include + +#include "up_arch.h" + +#include +#include +#include +#include +#include + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define WTCON 0x0000 +#define WTDAT 0x0004 +#define WTCNT 0x0008 +#define WTCLRINT 0x000C + +#define WTCON_RESET_MASK (1 << 0) +#define WTCON_RESET_DIS (0 << 0) +#define WTCON_RESET_EN (1 << 0) + +#define WTCON_IRQ_MASK (1 << 2) +#define WTCON_IRQ_DIS (0 << 2) +#define WTCON_IRQ_EN (1 << 2) + +#define WTCON_CLK_DIV_MASK (3 << 3) +#define WTCON_CLK_DIV(x) ((x & 3) << 3) + +#define WTCON_EN_MASK (1 << 5) +#define WTCON_DIS (0 << 5) +#define WTCON_EN (1 << 5) + +#define WTCON_PRESCALER_MASK (0xF << 8) +#define WTCON_PRESCALER(x) ((x & 0xF) << 8) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s5j_watchdog_disable + * + * Description: + * Disable the watchdog timer. The S5J always boots with the watchdog + * timer enabled at timeout of 10 - 20 seconds by the second stage boot + * loader to detect any boot failure. So, the watchdog timer must be + * disabled as part of the start up logic. + * + ****************************************************************************/ +void s5j_watchdog_disable(void) +{ + unsigned int wtcon = (getreg32(S5J_WDT_BASE + WTCON) & ~WTCON_EN_MASK) | WTCON_DIS; + putreg32(wtcon, S5J_WDT_BASE + WTCON); +} + +#ifdef CONFIG_S5J_WATCHDOG +/**************************************************************************** + * Name: s5j_watchdog_enable + * + * Description: + * Enable watchdog operation. + * Should be correctly configured before enabling. + * + ****************************************************************************/ +void s5j_watchdog_enable(void) +{ + unsigned int wtcon = (getreg32(S5J_WDT_BASE + WTCON) & ~WTCON_EN_MASK) | WTCON_EN; + putreg32(wtcon, S5J_WDT_BASE + WTCON); +} + +/**************************************************************************** + * Name: s5j_watchdog_reset_disable + * + * Description: + * When WD timer expires, it can issue HW reset. + * This function disables reset feature. + * Watchdog will be reloaded with value written in reload register. + * and continue its operation. + * + ****************************************************************************/ +void s5j_watchdog_reset_disable(void) +{ + unsigned int wtcon = (getreg32(S5J_WDT_BASE + WTCON) & ~WTCON_RESET_MASK) | WTCON_RESET_DIS; + putreg32(wtcon, S5J_WDT_BASE + WTCON); +} + +/**************************************************************************** + * Name: s5j_watchdog_reset_enable + * + * Description: + * When WD timer expires, it can issue HW reset. + * This function enables reset feature. + * + ****************************************************************************/ +void s5j_watchdog_reset_enable(void) +{ + unsigned int wtcon = (getreg32(S5J_WDT_BASE + WTCON) & ~WTCON_RESET_MASK) | WTCON_RESET_EN; + putreg32(wtcon, S5J_WDT_BASE + WTCON); +} + +/**************************************************************************** + * Name: s5j_watchdog_irq_disable + * + * Description: + * When WD timer expires, it can issue interrupt. + * This function disables reset feature. + * + ****************************************************************************/ +void s5j_watchdog_irq_disable(void) +{ + unsigned int wtcon = (getreg32(S5J_WDT_BASE + WTCON) & ~WTCON_IRQ_MASK) | WTCON_IRQ_DIS; + putreg32(wtcon, S5J_WDT_BASE + WTCON); +} + +/**************************************************************************** + * Name: s5j_watchdog_irq_enable + * + * Description: + * When WD timer expires, it can issue interrupt. + * This function enables reset feature. + * + ****************************************************************************/ +void s5j_watchdog_irq_enable(void) +{ + unsigned int wtcon = (getreg32(S5J_WDT_BASE + WTCON) & ~WTCON_IRQ_MASK) | WTCON_IRQ_EN; + putreg32(wtcon, S5J_WDT_BASE + WTCON); +} + +/**************************************************************************** + * Name: s5j_watchdog_clk_set + * + * Description: + * WD timer clock can be defined by prescaler and divider. + * WD frequency can be calculated by next equation: + * WD_CLK = CLK_IN/((prescaler+1)*divider) + * Where: + * CLK_IN - input clock frequency (by default 26MHz), + * prescaler - 8 bit value 0~255, + * divider - 2 bit division factor, + * encoding 0 - 16, 1 - 32, 2 - 64, 3 - 128 division ratios. + * + ****************************************************************************/ +void s5j_watchdog_clk_set(unsigned int prescaler, unsigned int divider) +{ + unsigned int wtcon = getreg32(S5J_WDT_BASE + WTCON); + + wtcon &= ~(WTCON_PRESCALER_MASK | WTCON_CLK_DIV_MASK); + wtcon |= WTCON_CLK_DIV(divider) | WTCON_PRESCALER(prescaler); + + putreg32(wtcon, S5J_WDT_BASE + WTCON); +} + +/**************************************************************************** + * Name: s5j_watchdog_set_reload_val + * + * Description: + * When WD timer expires, if reset is disabled, will be reloaded with value + * defined by this function call. + * + ****************************************************************************/ +void s5j_watchdog_set_reload_val(unsigned int reload_val) +{ + putreg32(reload_val, S5J_WDT_BASE + WTDAT); +} + +/**************************************************************************** + * Name: s5j_watchdog_get_curr + * + * Description: + * Function s5j_watchdog_get_curr returns current WD counter value. + ****************************************************************************/ +unsigned int s5j_watchdog_get_curr(void) +{ + return getreg32(S5J_WDT_BASE + WTCNT); +} + +/**************************************************************************** + * Name: s5j_watchdog_set_curr + * + * Description: + * Function s5j_watchdog_set_curr sets immediately current WD counter value. + * Use this function to set initial WD timer value before running operation. + ****************************************************************************/ +void s5j_watchdog_set_curr(unsigned int curr_val) +{ + putreg32(curr_val, S5J_WDT_BASE + WTCNT); +} + +/**************************************************************************** + * Name: s5j_watchdog_clear_int + * + * Description: + * Function s5j_watchdog_clear_int clears pending interrupt flag. + * Used after WD IRQ service routine completes its operation. + ****************************************************************************/ +void s5j_watchdog_clear_int(void) +{ + putreg32(0xffffffff, S5J_WDT_BASE + WTCLRINT); +} +#endif