From: ths Date: Sat, 23 Jun 2007 18:04:12 +0000 (+0000) Subject: Handle MIPS64 SEGBITS value correctly. X-Git-Tag: TizenStudio_2.0_p2.3~13210 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e034e2c39aee1800101812045690e0575abb428b;p=sdk%2Femulator%2Fqemu.git Handle MIPS64 SEGBITS value correctly. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3011 c046a42c-6fe2-441c-8c8c-71466251a162 --- diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 7650be4..f5f35e1 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -102,6 +102,8 @@ struct CPUMIPSState { uint32_t nb_tlb; uint32_t tlb_in_use; + uint32_t SEGBITS; + target_ulong SEGMask; int (*map_address) (CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type); void (*do_tlbwi) (void); void (*do_tlbwr) (void); diff --git a/target-mips/helper.c b/target-mips/helper.c index 9da6212..87a6a33 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -77,7 +77,7 @@ int r4k_map_address (CPUState *env, target_ulong *physical, int *prot, target_ulong tag = address & ~mask; target_ulong VPN = tlb->VPN & ~mask; #ifdef TARGET_MIPS64 - tag &= 0xC00000FFFFFFFFFFULL; + tag &= env->SEGMask; #endif /* Check ASID, virtual page number & size */ @@ -140,18 +140,17 @@ static int get_physical_address (CPUState *env, target_ulong *physical, /* XXX: Assuming : - PABITS = 36 (correct for MIPS64R1) - - SEGBITS = 40 */ } else if (address < 0x3FFFFFFFFFFFFFFFULL) { /* xuseg */ - if (UX && address < 0x000000FFFFFFFFFFULL) { + if (UX && address < (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { ret = env->map_address(env, physical, prot, address, rw, access_type); } else { ret = TLBRET_BADADDR; } } else if (address < 0x7FFFFFFFFFFFFFFFULL) { /* xsseg */ - if (SX && address < 0x400000FFFFFFFFFFULL) { + if (SX && address < (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { ret = env->map_address(env, physical, prot, address, rw, access_type); } else { ret = TLBRET_BADADDR; @@ -159,9 +158,9 @@ static int get_physical_address (CPUState *env, target_ulong *physical, } else if (address < 0xBFFFFFFFFFFFFFFFULL) { /* xkphys */ /* XXX: check supervisor mode */ - if (KX && (address & 0x03FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL) + if (KX && (address & 0x07FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL) { - *physical = address & 0X000000FFFFFFFFFFULL; + *physical = address & 0X0000000FFFFFFFFFULL; *prot = PAGE_READ | PAGE_WRITE; } else { ret = TLBRET_BADADDR; @@ -169,7 +168,7 @@ static int get_physical_address (CPUState *env, target_ulong *physical, } else if (address < 0xFFFFFFFF7FFFFFFFULL) { /* xkseg */ /* XXX: check supervisor mode */ - if (KX && address < 0xC00000FF7FFFFFFFULL) { + if (KX && address < (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { ret = env->map_address(env, physical, prot, address, rw, access_type); } else { ret = TLBRET_BADADDR; @@ -303,10 +302,10 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, env->CP0_EntryHi = (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); #ifdef TARGET_MIPS64 - env->CP0_EntryHi &= 0xc00000ffffffffffULL; - env->CP0_XContext = (env->CP0_XContext & 0xfffffffe00000000ULL) | - ((address >> 31) & 0x0000000180000000ULL) | - ((address >> 9) & 0x000000007ffffff0ULL); + env->CP0_EntryHi &= env->SEGMask; + env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | + ((address & 0xC00000000000ULL) >> (env->SEGBITS - 9)) | + ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9); #endif env->exception_index = exception; env->error_code = error_code; @@ -555,7 +554,7 @@ void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra) if (tlb->V0) { addr = tlb->VPN & ~mask; #ifdef TARGET_MIPS64 - if (addr >= 0xC00000FF80000000ULL) { + if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { addr |= 0x3FFFFF0000000000ULL; } #endif @@ -568,7 +567,7 @@ void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra) if (tlb->V1) { addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); #ifdef TARGET_MIPS64 - if (addr >= 0xC00000FF80000000ULL) { + if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { addr |= 0x3FFFFF0000000000ULL; } #endif diff --git a/target-mips/op.c b/target-mips/op.c index 66e27e2..715c355 100644 --- a/target-mips/op.c +++ b/target-mips/op.c @@ -1328,7 +1328,7 @@ void op_mtc0_entryhi (void) /* 1k pages not implemented */ val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF); #ifdef TARGET_MIPS64 - val = T0 & 0xC00000FFFFFFFFFFULL; + val &= env->SEGMask; #endif old = env->CP0_EntryHi; env->CP0_EntryHi = val; @@ -1526,7 +1526,8 @@ void op_mtc0_desave (void) #ifdef TARGET_MIPS64 void op_mtc0_xcontext (void) { - env->CP0_XContext = (env->CP0_XContext & 0x1ffffffffULL) | (T0 & ~0x1ffffffffULL); + target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; + env->CP0_XContext = (env->CP0_XContext & mask) | (T0 & ~mask); RETURN(); } diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index c169beb..e4f2676 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -374,7 +374,7 @@ static void r4k_fill_tlb (int idx) tlb = &env->mmu.r4k.tlb[idx]; tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); #ifdef TARGET_MIPS64 - tlb->VPN &= 0xC00000FFFFFFFFFFULL; + tlb->VPN &= env->SEGMask; #endif tlb->ASID = env->CP0_EntryHi & 0xFF; tlb->PageMask = env->CP0_PageMask; diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 5d25e57..687e3e5 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -71,6 +71,7 @@ struct mips_def_t { int32_t CCRes; int32_t Status_rw_bitmask; int32_t CP1_fcr0; + int32_t SEGBITS; }; /*****************************************************************************/ @@ -87,6 +88,7 @@ static mips_def_t mips_defs[] = .SYNCI_Step = 32, .CCRes = 2, .Status_rw_bitmask = 0x3278FF17, + .SEGBITS = 32, }, { .name = "4KEcR1", @@ -98,6 +100,7 @@ static mips_def_t mips_defs[] = .SYNCI_Step = 32, .CCRes = 2, .Status_rw_bitmask = 0x3278FF17, + .SEGBITS = 32, }, { .name = "4KEc", @@ -109,6 +112,7 @@ static mips_def_t mips_defs[] = .SYNCI_Step = 32, .CCRes = 2, .Status_rw_bitmask = 0x3278FF17, + .SEGBITS = 32, }, { .name = "24Kc", @@ -120,6 +124,7 @@ static mips_def_t mips_defs[] = .SYNCI_Step = 32, .CCRes = 2, .Status_rw_bitmask = 0x3278FF17, + .SEGBITS = 32, }, { .name = "24Kf", @@ -133,6 +138,7 @@ static mips_def_t mips_defs[] = .Status_rw_bitmask = 0x3678FF17, .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), + .SEGBITS = 32, }, #ifdef TARGET_MIPS64 { @@ -147,6 +153,7 @@ static mips_def_t mips_defs[] = .Status_rw_bitmask = 0x3678FFFF, /* The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */ .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), + .SEGBITS = 40, }, { .name = "5Kc", @@ -161,6 +168,7 @@ static mips_def_t mips_defs[] = .SYNCI_Step = 32, .CCRes = 2, .Status_rw_bitmask = 0x32F8FFFF, + .SEGBITS = 42, }, { .name = "5Kf", @@ -178,6 +186,7 @@ static mips_def_t mips_defs[] = /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */ .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | (0x81 << FCR0_PRID) | (0x0 << FCR0_REV), + .SEGBITS = 42, }, { .name = "20Kc", @@ -198,6 +207,7 @@ static mips_def_t mips_defs[] = .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | (1 << FCR0_D) | (1 << FCR0_S) | (0x82 << FCR0_PRID) | (0x0 << FCR0_REV), + .SEGBITS = 40, }, #endif }; @@ -274,6 +284,10 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def) env->CCRes = def->CCRes; env->Status_rw_bitmask = def->Status_rw_bitmask; env->fcr0 = def->CP1_fcr0; +#ifdef TARGET_MIPS64 + env->SEGBITS = def->SEGBITS; + env->SEGMask = (3ULL << 62) | ((1ULL << def->SEGBITS) - 1); +#endif #ifdef CONFIG_USER_ONLY if (env->CP0_Config1 & (1 << CP0C1_FP)) env->hflags |= MIPS_HFLAG_FPU;