From: Craig Topper <craig.topper@intel.com>
Date: Tue, 23 Oct 2018 21:58:49 +0000 (+0000)
Subject: [X86] Autogenerate comple checks. NFC
X-Git-Tag: llvmorg-8.0.0-rc1~5981
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e01d516ac7dabdd2fc5de015c344669a8d93cc2e;p=platform%2Fupstream%2Fllvm.git

[X86] Autogenerate comple checks. NFC

llvm-svn: 345087
---

diff --git a/llvm/test/CodeGen/X86/crash-O0.ll b/llvm/test/CodeGen/X86/crash-O0.ll
index dab15c1..1a234d4 100644
--- a/llvm/test/CodeGen/X86/crash-O0.ll
+++ b/llvm/test/CodeGen/X86/crash-O0.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -O0 -relocation-model=pic -disable-fp-elim < %s | FileCheck %s
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin10"
@@ -9,6 +10,35 @@ target triple = "x86_64-apple-darwin10"
 ; aliased registers (AX and AL) - RegAllocFast does not like that.
 ; PR7312
 define i32 @div8() nounwind {
+; CHECK-LABEL: div8:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    pushq %rbp
+; CHECK-NEXT:    movq %rsp, %rbp
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    movb %al, %cl
+; CHECK-NEXT:    ## implicit-def: $rdx
+; CHECK-NEXT:    movb %dl, %sil
+; CHECK-NEXT:    movzbw %cl, %ax
+; CHECK-NEXT:    divb %sil
+; CHECK-NEXT:    movb %al, {{[-0-9]+}}(%r{{[sb]}}p) ## 1-byte Spill
+; CHECK-NEXT:    movzbw %cl, %ax
+; CHECK-NEXT:    divb %sil
+; CHECK-NEXT:    shrw $8, %ax
+; CHECK-NEXT:    movb %al, %cl
+; CHECK-NEXT:    cmpb %sil, %cl
+; CHECK-NEXT:    jae LBB0_2
+; CHECK-NEXT:  ## %bb.1: ## %"39"
+; CHECK-NEXT:    movb {{[-0-9]+}}(%r{{[sb]}}p), %al ## 1-byte Reload
+; CHECK-NEXT:    movzbl %al, %ecx
+; CHECK-NEXT:    ## implicit-def: $edx
+; CHECK-NEXT:    imull %edx, %ecx
+; CHECK-NEXT:    addl %edx, %ecx
+; CHECK-NEXT:    cmpl %edx, %ecx
+; CHECK-NEXT:    je LBB0_3
+; CHECK-NEXT:  LBB0_2: ## %"40"
+; CHECK-NEXT:    ud2
+; CHECK-NEXT:  LBB0_3: ## %"41"
+; CHECK-NEXT:    ud2
 entry:
   %0 = trunc i64 undef to i8                      ; <i8> [#uses=3]
   %1 = udiv i8 0, %0                              ; <i8> [#uses=1]
@@ -38,12 +68,22 @@ entry:
 ; An instruction gets between CQO and DIV64 because the load is folded
 ; into the division but it requires a sign extension.
 ; PR21700
-; CHECK-LABEL: addressModeWith32bitIndex:
-; CHECK: cqto
-; CHECK-NEXT: movslq
-; CHECK-NEXT: idivq
-; CHECK: retq
 define i64 @addressModeWith32bitIndex(i32 %V) {
+; CHECK-LABEL: addressModeWith32bitIndex:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    pushq %rbp
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset %rbp, -16
+; CHECK-NEXT:    movq %rsp, %rbp
+; CHECK-NEXT:    .cfi_def_cfa_register %rbp
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    movq %rcx, %rax
+; CHECK-NEXT:    cqto
+; CHECK-NEXT:    movslq %edi, %rsi
+; CHECK-NEXT:    idivq (%rcx,%rsi,8)
+; CHECK-NEXT:    popq %rbp
+; CHECK-NEXT:    retq
   %gep = getelementptr i64, i64* null, i32 %V
   %load = load i64, i64* %gep
   %sdiv = sdiv i64 0, %load