From: Eric Anholt Date: Tue, 7 Nov 2017 17:51:56 +0000 (-0800) Subject: broadcom/vc5: Fix scheduling for a non-SFU R4 write after a dead R4 write. X-Git-Tag: upstream/18.1.0~4374 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=dfff9ce45ef9e2ba61814d7a75b896bbaf970557;p=platform%2Fupstream%2Fmesa.git broadcom/vc5: Fix scheduling for a non-SFU R4 write after a dead R4 write. The v3d_qpu_writes_r*() were only checking for fixed-function accumulator writes, not normal ALU writes to those regs. Fixes fs-discard-exit-2 on simulation (but not HW). --- diff --git a/src/broadcom/compiler/qpu_schedule.c b/src/broadcom/compiler/qpu_schedule.c index dd221e0..799da80 100644 --- a/src/broadcom/compiler/qpu_schedule.c +++ b/src/broadcom/compiler/qpu_schedule.c @@ -201,13 +201,15 @@ process_waddr_deps(struct schedule_state *state, struct schedule_node *n, case V3D_QPU_WADDR_R0: case V3D_QPU_WADDR_R1: case V3D_QPU_WADDR_R2: - case V3D_QPU_WADDR_R3: - case V3D_QPU_WADDR_R4: - case V3D_QPU_WADDR_R5: add_write_dep(state, &state->last_r[waddr - V3D_QPU_WADDR_R0], n); break; + case V3D_QPU_WADDR_R3: + case V3D_QPU_WADDR_R4: + case V3D_QPU_WADDR_R5: + /* Handled by v3d_qpu_writes_r*() checks below. */ + break; case V3D_QPU_WADDR_VPM: case V3D_QPU_WADDR_VPMU: diff --git a/src/broadcom/qpu/qpu_instr.c b/src/broadcom/qpu/qpu_instr.c index 7499170..7695e0b 100644 --- a/src/broadcom/qpu/qpu_instr.c +++ b/src/broadcom/qpu/qpu_instr.c @@ -602,6 +602,18 @@ v3d_qpu_magic_waddr_is_tsy(enum v3d_qpu_waddr waddr) bool v3d_qpu_writes_r3(const struct v3d_qpu_instr *inst) { + if (inst->type == V3D_QPU_INSTR_TYPE_ALU) { + if (inst->alu.add.magic_write && + inst->alu.add.waddr == V3D_QPU_WADDR_R3) { + return true; + } + + if (inst->alu.mul.magic_write && + inst->alu.mul.waddr == V3D_QPU_WADDR_R3) { + return true; + } + } + return inst->sig.ldvary || inst->sig.ldvpm; } @@ -613,12 +625,14 @@ v3d_qpu_writes_r4(const struct v3d_qpu_instr *inst) if (inst->type == V3D_QPU_INSTR_TYPE_ALU) { if (inst->alu.add.magic_write && - v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr)) { + (inst->alu.add.waddr == V3D_QPU_WADDR_R4 || + v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr))) { return true; } if (inst->alu.mul.magic_write && - v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr)) { + (inst->alu.mul.waddr == V3D_QPU_WADDR_R4 || + v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr))) { return true; } } @@ -629,6 +643,18 @@ v3d_qpu_writes_r4(const struct v3d_qpu_instr *inst) bool v3d_qpu_writes_r5(const struct v3d_qpu_instr *inst) { + if (inst->type == V3D_QPU_INSTR_TYPE_ALU) { + if (inst->alu.add.magic_write && + inst->alu.add.waddr == V3D_QPU_WADDR_R5) { + return true; + } + + if (inst->alu.mul.magic_write && + inst->alu.mul.waddr == V3D_QPU_WADDR_R5) { + return true; + } + } + return inst->sig.ldvary || inst->sig.ldunif; }