From: Sanjay Patel <spatel@rotateright.com>
Date: Sun, 31 May 2020 15:06:32 +0000 (-0400)
Subject: [utils] update expected strings in tests; NFC
X-Git-Tag: llvmorg-12-init~4554
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=dfbfdc96f9e15be40c938cde9b159afd028bf4a2;p=platform%2Fupstream%2Fllvm.git

[utils] update expected strings in tests; NFC

The script was changes with:
https://github.com/llvm/llvm-project/commit/bfdc2552664d6f0bb332a9c6a115877020f3c1df
---

diff --git a/clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.expected b/clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.expected
index d6ba7ae..6ea1542 100644
--- a/clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.expected
+++ b/clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.expected
@@ -8,10 +8,10 @@
 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
 // CHECK-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
 // CHECK-NEXT:    store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
-// CHECK-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
-// CHECK-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
-// CHECK-NEXT:    [[CONV:%.*]] = sext i32 [[TMP1]] to i64
-// CHECK-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]]
+// CHECK-NEXT:    [[NAMELESS0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// CHECK-NEXT:    [[NAMELESS1:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// CHECK-NEXT:    [[CONV:%.*]] = sext i32 [[NAMELESS1]] to i64
+// CHECK-NEXT:    [[ADD:%.*]] = add nsw i64 [[NAMELESS0]], [[CONV]]
 // CHECK-NEXT:    ret i64 [[ADD]]
 //
 long test(long a, int b) {
@@ -27,12 +27,12 @@ long test(long a, int b) {
 // CHECK-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
 // CHECK-NEXT:    store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
 // CHECK-NEXT:    store i32 [[C:%.*]], i32* [[C_ADDR]], align 4
-// CHECK-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
-// CHECK-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
-// CHECK-NEXT:    [[CONV:%.*]] = sext i32 [[TMP1]] to i64
-// CHECK-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]]
-// CHECK-NEXT:    [[TMP2:%.*]] = load i32, i32* [[C_ADDR]], align 4
-// CHECK-NEXT:    [[CONV1:%.*]] = sext i32 [[TMP2]] to i64
+// CHECK-NEXT:    [[NAMELESS0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// CHECK-NEXT:    [[NAMELESS1:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// CHECK-NEXT:    [[CONV:%.*]] = sext i32 [[NAMELESS1]] to i64
+// CHECK-NEXT:    [[ADD:%.*]] = add nsw i64 [[NAMELESS0]], [[CONV]]
+// CHECK-NEXT:    [[NAMELESS2:%.*]] = load i32, i32* [[C_ADDR]], align 4
+// CHECK-NEXT:    [[CONV1:%.*]] = sext i32 [[NAMELESS2]] to i64
 // CHECK-NEXT:    [[ADD2:%.*]] = add nsw i64 [[ADD]], [[CONV1]]
 // CHECK-NEXT:    ret i64 [[ADD2]]
 //
diff --git a/clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.funcsig.expected b/clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.funcsig.expected
index 005b2f2..dbe1296 100644
--- a/clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.funcsig.expected
+++ b/clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.funcsig.expected
@@ -9,10 +9,10 @@
 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
 // CHECK-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
 // CHECK-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
-// CHECK-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
-// CHECK-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
-// CHECK-NEXT:    [[CONV:%.*]] = sext i32 [[TMP1]] to i64
-// CHECK-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]]
+// CHECK-NEXT:    [[NAMELESS0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// CHECK-NEXT:    [[NAMELESS1:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// CHECK-NEXT:    [[CONV:%.*]] = sext i32 [[NAMELESS1]] to i64
+// CHECK-NEXT:    [[ADD:%.*]] = add nsw i64 [[NAMELESS0]], [[CONV]]
 // CHECK-NEXT:    ret i64 [[ADD]]
 //
 long test(long a, int b) {
@@ -29,12 +29,12 @@ long test(long a, int b) {
 // CHECK-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
 // CHECK-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
 // CHECK-NEXT:    store i32 [[C]], i32* [[C_ADDR]], align 4
-// CHECK-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
-// CHECK-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
-// CHECK-NEXT:    [[CONV:%.*]] = sext i32 [[TMP1]] to i64
-// CHECK-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]]
-// CHECK-NEXT:    [[TMP2:%.*]] = load i32, i32* [[C_ADDR]], align 4
-// CHECK-NEXT:    [[CONV1:%.*]] = sext i32 [[TMP2]] to i64
+// CHECK-NEXT:    [[NAMELESS0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// CHECK-NEXT:    [[NAMELESS1:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// CHECK-NEXT:    [[CONV:%.*]] = sext i32 [[NAMELESS1]] to i64
+// CHECK-NEXT:    [[ADD:%.*]] = add nsw i64 [[NAMELESS0]], [[CONV]]
+// CHECK-NEXT:    [[NAMELESS2:%.*]] = load i32, i32* [[C_ADDR]], align 4
+// CHECK-NEXT:    [[CONV1:%.*]] = sext i32 [[NAMELESS2]] to i64
 // CHECK-NEXT:    [[ADD2:%.*]] = add nsw i64 [[ADD]], [[CONV1]]
 // CHECK-NEXT:    ret i64 [[ADD2]]
 //