From: Vinay Belgaumkar Date: Fri, 15 Apr 2022 22:40:23 +0000 (-0700) Subject: drm/i915/guc: Apply Wa_16011777198 X-Git-Tag: v6.6.17~3937^2~16^2~895 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=dfa57ecf77c66eb28ac7760f582bfd7d4183c429;p=platform%2Fkernel%2Flinux-rpi.git drm/i915/guc: Apply Wa_16011777198 Enable GuC Wa to reset RCS/CCS before it goes into RC6. Signed-off-by: Vinay Belgaumkar Reviewed-by: John Harrison Signed-off-by: John Harrison Link: https://patchwork.freedesktop.org/patch/msgid/20220415224025.3693037-5-umesh.nerlige.ramappa@intel.com --- diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index fd04c4c..8308893 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -310,6 +310,11 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) if (GRAPHICS_VER(gt->i915) == 12) flags |= GUC_WA_PRE_PARSER; + /* Wa_16011777198:dg2 */ + if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || + IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) + flags |= GUC_WA_RCS_RESET_BEFORE_RC6; + return flags; } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h index fe5751f..126e67e 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h @@ -100,6 +100,7 @@ #define GUC_CTL_WA 1 #define GUC_WA_GAM_CREDITS BIT(10) #define GUC_WA_DUAL_QUEUE BIT(11) +#define GUC_WA_RCS_RESET_BEFORE_RC6 BIT(13) #define GUC_WA_PRE_PARSER BIT(14) #define GUC_WA_POLLCS BIT(18)