From: Kenneth Graunke Date: Sat, 18 Feb 2012 21:08:29 +0000 (-0800) Subject: i965: Make the dummy fragment shader work in SIMD16 mode. X-Git-Tag: 062012170305~1473 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=df5963c25641a7c3a4bbfcb81cc3dc771581590e;p=profile%2Fivi%2Fmesa.git i965: Make the dummy fragment shader work in SIMD16 mode. If you're resorting to the dummy shader, you've probably already turned off SIMD16 mode. But if you didn't, it would die in a fire. We could either fail to compile in SIMD16 mode...or just fix it. Signed-off-by: Kenneth Graunke Reviewed-by: Eric Anholt --- diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index f9b3064..15eae43 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -1800,16 +1800,18 @@ fs_visitor::emit(fs_inst inst) void fs_visitor::emit_dummy_fs() { + int reg_width = c->dispatch_width / 8; + /* Everyone's favorite color. */ - emit(BRW_OPCODE_MOV, fs_reg(MRF, 2), fs_reg(1.0f)); - emit(BRW_OPCODE_MOV, fs_reg(MRF, 3), fs_reg(0.0f)); - emit(BRW_OPCODE_MOV, fs_reg(MRF, 4), fs_reg(1.0f)); - emit(BRW_OPCODE_MOV, fs_reg(MRF, 5), fs_reg(0.0f)); + emit(BRW_OPCODE_MOV, fs_reg(MRF, 2 + 0 * reg_width), fs_reg(1.0f)); + emit(BRW_OPCODE_MOV, fs_reg(MRF, 2 + 1 * reg_width), fs_reg(0.0f)); + emit(BRW_OPCODE_MOV, fs_reg(MRF, 2 + 2 * reg_width), fs_reg(1.0f)); + emit(BRW_OPCODE_MOV, fs_reg(MRF, 2 + 3 * reg_width), fs_reg(0.0f)); fs_inst *write; write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0)); write->base_mrf = 2; - write->mlen = 4; + write->mlen = 4 * reg_width; write->eot = true; }