From: Lucas Stach Date: Tue, 8 Nov 2016 16:55:36 +0000 (+0100) Subject: ARM: dts: imx6qp: correct LDB clock inputs X-Git-Tag: v4.14-rc1~1857^2~10^2~2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=df38e42f9da9ad731c287963f012bee46cf01169;p=platform%2Fkernel%2Flinux-rpi.git ARM: dts: imx6qp: correct LDB clock inputs On i.MX6QP the LDB clock tree has changed to move the clk gate before the divider, to prevent clock glitches propagating downstream. A consequence of this change is that the clk divider is now the parent of the LDB inputs. Reflect this change in the devicetree to allow the LDB driver to properly configure the display clocks. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi index 886dbf2..caaa040 100644 --- a/arch/arm/boot/dts/imx6qp.dtsi +++ b/arch/arm/boot/dts/imx6qp.dtsi @@ -87,3 +87,13 @@ }; }; }; + +&ldb { + clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>; + clock-names = "di0_pll", "di1_pll", + "di0_sel", "di1_sel", "di2_sel", "di3_sel", + "di0", "di1"; +};