From: Trent Piepho Date: Tue, 1 Oct 2013 20:14:57 +0000 (-0700) Subject: spi: spi-mxs: Fix extra CS pulses and read mode in multi-transfer messages X-Git-Tag: v5.15~19014^2~13^2~8 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=df23286e57ceefe427d7ff925193283a8fafe9f3;p=platform%2Fkernel%2Flinux-starfive.git spi: spi-mxs: Fix extra CS pulses and read mode in multi-transfer messages There are two bits which control the CS line in the CTRL0 register: LOCK_CS and IGNORE_CRC. The latter would be better named DEASSERT_CS in SPI mode. Setting DEASSERT_CS causes CS to be de-asserted at the end of the transfer. It should normally be set only for the final segment of the final transfer. The DMA code explicitly sets it in this case, but because it never clears the bit from the ctrl0 register, it will remain set for all transfers in subsequent messages. This results in a CS pulse between transfers. There is a similar problem with the read mode bit never being cleared in DMA mode. This patch fixes DEASSERT_CS and READ being left on in DMA mode. Signed-off-by: Trent Piepho Cc: Marek Vasut Cc: Fabio Estevam Cc: Shawn Guo Signed-off-by: Mark Brown --- diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c index 090930a..68ea507 100644 --- a/drivers/spi/spi-mxs.c +++ b/drivers/spi/spi-mxs.c @@ -218,7 +218,8 @@ static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs, INIT_COMPLETION(spi->c); ctrl0 = readl(ssp->base + HW_SSP_CTRL0); - ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT; + ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC | + BM_SSP_CTRL0_READ); ctrl0 |= BM_SSP_CTRL0_DATA_XFER | mxs_spi_cs_to_reg(cs); if (!(flags & TXRX_WRITE))