From: Chris Packham <chris.packham@alliedtelesis.co.nz>
Date: Thu, 26 May 2022 01:29:46 +0000 (+1200)
Subject: dt-bindings: gpio: gpio-mvebu: document offset and marvell,pwm-offset
X-Git-Tag: v6.6.17~6894^2~47
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=df08a6fc0d5d7dd579dd0902893a433765d9f4c5;p=platform%2Fkernel%2Flinux-rpi.git

dt-bindings: gpio: gpio-mvebu: document offset and marvell,pwm-offset

The offset and marvell,pwm-offset properties weren't in the old binding.
Add them based on the existing usage in the driver and board DTS when
the marvell,armada-8k-gpio compatible is used.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
---

diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml b/Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml
index 459ec358..f1bd1e6 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml
+++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml
@@ -45,6 +45,10 @@ properties:
       - const: pwm
     minItems: 1
 
+  offset:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Offset in the register map for the gpio registers (in bytes)
+
   interrupts:
     description: |
       The list of interrupts that are used for all the pins managed by this
@@ -68,6 +72,10 @@ properties:
   "#gpio-cells":
     const: 2
 
+  marvell,pwm-offset:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Offset in the register map for the pwm registers (in bytes)
+
   "#pwm-cells":
     description:
       The first cell is the GPIO line number. The second cell is the period