From: Olof Johansson <olof@lixom.net>
Date: Mon, 17 Oct 2011 23:39:24 +0000 (-0700)
Subject: ARM: tegra: fuse: add bct strapping reading
X-Git-Tag: v3.4-rc1~73^2~11^2~17
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=dee47183301983139fd0ed784d0defe0ba08f8f6;p=profile%2Fivi%2Fkernel-adaptation-intel-automotive.git

ARM: tegra: fuse: add bct strapping reading

This is used by the memory setup code to pick the right memory
timing table, if needed.

Signed-off-by: Olof Johansson <olof@lixom.net>
---

diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index b1895c5..17fdd40 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -35,6 +35,17 @@ int tegra_cpu_process_id;
 int tegra_core_process_id;
 enum tegra_revision tegra_revision;
 
+/* The BCT to use at boot is specified by board straps that can be read
+ * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
+ */
+int tegra_bct_strapping;
+
+#define STRAP_OPT 0x008
+#define GMI_AD0 (1 << 4)
+#define GMI_AD1 (1 << 5)
+#define RAM_ID_MASK (GMI_AD0 | GMI_AD1)
+#define RAM_CODE_SHIFT 4
+
 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
 	[TEGRA_REVISION_UNKNOWN] = "unknown",
 	[TEGRA_REVISION_A01]     = "A01",
@@ -93,6 +104,9 @@ void tegra_init_fuse(void)
 	reg = tegra_fuse_readl(FUSE_SPARE_BIT);
 	tegra_core_process_id = (reg >> 12) & 3;
 
+	reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
+	tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
+
 	tegra_revision = tegra_get_revision();
 
 	pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index 7576aaf..d65d2ab 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -40,6 +40,8 @@ extern int tegra_cpu_process_id;
 extern int tegra_core_process_id;
 extern enum tegra_revision tegra_revision;
 
+extern int tegra_bct_strapping;
+
 unsigned long long tegra_chip_uid(void);
 void tegra_init_fuse(void);