From: Ju-Zhe Zhong Date: Mon, 6 Feb 2023 05:12:38 +0000 (+0800) Subject: RISC-V: Add vsext.vf8 C API tests X-Git-Tag: upstream/13.1.0~1395 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=decfa1d5bc5878dbd77db4c523da49868de2057a;p=platform%2Fupstream%2Fgcc.git RISC-V: Add vsext.vf8 C API tests gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vsext_vf8-1.c: New test. * gcc.target/riscv/rvv/base/vsext_vf8-2.c: New test. * gcc.target/riscv/rvv/base/vsext_vf8-3.c: New test. * gcc.target/riscv/rvv/base/vsext_vf8_m-1.c: New test. * gcc.target/riscv/rvv/base/vsext_vf8_m-2.c: New test. * gcc.target/riscv/rvv/base/vsext_vf8_m-3.c: New test. * gcc.target/riscv/rvv/base/vsext_vf8_mu-1.c: New test. * gcc.target/riscv/rvv/base/vsext_vf8_mu-2.c: New test. * gcc.target/riscv/rvv/base/vsext_vf8_mu-3.c: New test. * gcc.target/riscv/rvv/base/vsext_vf8_tu-1.c: New test. * gcc.target/riscv/rvv/base/vsext_vf8_tu-2.c: New test. * gcc.target/riscv/rvv/base/vsext_vf8_tu-3.c: New test. * gcc.target/riscv/rvv/base/vsext_vf8_tum-1.c: New test. * gcc.target/riscv/rvv/base/vsext_vf8_tum-2.c: New test. * gcc.target/riscv/rvv/base/vsext_vf8_tum-3.c: New test. * gcc.target/riscv/rvv/base/vsext_vf8_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vsext_vf8_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vsext_vf8_tumu-3.c: New test. --- diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8-1.c new file mode 100644 index 0000000..e922129 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8-1.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_i64m1(vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m1(op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf8_i64m2(vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m2(op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf8_i64m4(vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m4(op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf8_i64m8(vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m8(op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8-2.c new file mode 100644 index 0000000..c9b2815 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8-2.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_i64m1(vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m1(op1,31); +} + + +vint64m2_t test___riscv_vsext_vf8_i64m2(vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m2(op1,31); +} + + +vint64m4_t test___riscv_vsext_vf8_i64m4(vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m4(op1,31); +} + + +vint64m8_t test___riscv_vsext_vf8_i64m8(vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m8(op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8-3.c new file mode 100644 index 0000000..00db955 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8-3.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_i64m1(vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m1(op1,32); +} + + +vint64m2_t test___riscv_vsext_vf8_i64m2(vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m2(op1,32); +} + + +vint64m4_t test___riscv_vsext_vf8_i64m4(vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m4(op1,32); +} + + +vint64m8_t test___riscv_vsext_vf8_i64m8(vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m8(op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_m-1.c new file mode 100644 index 0000000..483bd5f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_m-1.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_i64m1_m(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m1_m(mask,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf8_i64m2_m(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m2_m(mask,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf8_i64m4_m(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m4_m(mask,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf8_i64m8_m(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m8_m(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_m-2.c new file mode 100644 index 0000000..31f7009 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_m-2.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_i64m1_m(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m1_m(mask,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf8_i64m2_m(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m2_m(mask,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf8_i64m4_m(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m4_m(mask,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf8_i64m8_m(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m8_m(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_m-3.c new file mode 100644 index 0000000..ba388dd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_m-3.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_i64m1_m(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m1_m(mask,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf8_i64m2_m(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m2_m(mask,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf8_i64m4_m(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m4_m(mask,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf8_i64m8_m(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m8_m(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_mu-1.c new file mode 100644 index 0000000..c6fa150 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_mu-1.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m1_mu(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf8_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m2_mu(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf8_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m4_mu(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf8_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m8_mu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_mu-2.c new file mode 100644 index 0000000..1a0372f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_mu-2.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m1_mu(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf8_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m2_mu(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf8_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m4_mu(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf8_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m8_mu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_mu-3.c new file mode 100644 index 0000000..c2c0f1e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_mu-3.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m1_mu(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf8_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m2_mu(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf8_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m4_mu(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf8_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m8_mu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tu-1.c new file mode 100644 index 0000000..eb761d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tu-1.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_i64m1_tu(vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m1_tu(merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf8_i64m2_tu(vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m2_tu(merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf8_i64m4_tu(vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m4_tu(merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf8_i64m8_tu(vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m8_tu(merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tu-2.c new file mode 100644 index 0000000..c5dd47d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tu-2.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_i64m1_tu(vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m1_tu(merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf8_i64m2_tu(vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m2_tu(merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf8_i64m4_tu(vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m4_tu(merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf8_i64m8_tu(vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m8_tu(merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tu-3.c new file mode 100644 index 0000000..7a8b0af --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tu-3.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_i64m1_tu(vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m1_tu(merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf8_i64m2_tu(vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m2_tu(merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf8_i64m4_tu(vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m4_tu(merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf8_i64m8_tu(vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m8_tu(merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tum-1.c new file mode 100644 index 0000000..e195627 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tum-1.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m1_tum(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf8_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m2_tum(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf8_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m4_tum(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf8_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m8_tum(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tum-2.c new file mode 100644 index 0000000..db68ea6c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tum-2.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m1_tum(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf8_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m2_tum(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf8_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m4_tum(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf8_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m8_tum(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tum-3.c new file mode 100644 index 0000000..0a153fa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tum-3.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m1_tum(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf8_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m2_tum(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf8_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m4_tum(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf8_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m8_tum(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tumu-1.c new file mode 100644 index 0000000..95ec85a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tumu-1.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m1_tumu(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf8_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m2_tumu(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf8_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m4_tumu(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf8_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m8_tumu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tumu-2.c new file mode 100644 index 0000000..d6ef6e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tumu-2.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m1_tumu(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf8_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m2_tumu(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf8_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m4_tumu(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf8_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m8_tumu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tumu-3.c new file mode 100644 index 0000000..b04a1fb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tumu-3.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint64m1_t test___riscv_vsext_vf8_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m1_tumu(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf8_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m2_tumu(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf8_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m4_tumu(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf8_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf8_i64m8_tumu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */