From: Kumar Gala Date: Tue, 15 Feb 2011 04:45:48 +0000 (-0600) Subject: powerpc/85xx: Fix writing to spin table 'cpu-release-addr' on ppc64e X-Git-Tag: v2.6.39-rc1~430^2~15 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=decbb280bb8e3bceebcf5defb4f61dfbfdb23e18;p=platform%2Fupstream%2Fkernel-adaptation-pc.git powerpc/85xx: Fix writing to spin table 'cpu-release-addr' on ppc64e If the spin table is located in the linear mapping (which can happen if we have 4G or more of memory) we need to access the spin table via a cacheable coherent mapping like we do on ppc32 (and do explicit cache flush). See the following commit for the ppc32 version of this issue: commit d1d47ec6e62ab08d2ebb925fd9203abfad3adfbf Author: Peter Tyser Date: Fri Dec 18 16:50:37 2009 -0600 powerpc/85xx: Fix SMP when "cpu-release-addr" is in lowmem Signed-off-by: Kumar Gala --- diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c index 5c91a99..0d00ff9 100644 --- a/arch/powerpc/platforms/85xx/smp.c +++ b/arch/powerpc/platforms/85xx/smp.c @@ -91,10 +91,14 @@ smp_85xx_kick_cpu(int nr) while ((__secondary_hold_acknowledge != nr) && (++n < 1000)) mdelay(1); #else + smp_generic_kick_cpu(nr); + out_be64((u64 *)(bptr_vaddr + BOOT_ENTRY_ADDR_UPPER), __pa((u64)*((unsigned long long *) generic_secondary_smp_init))); - smp_generic_kick_cpu(nr); + if (!ioremappable) + flush_dcache_range((ulong)bptr_vaddr, + (ulong)(bptr_vaddr + SIZE_BOOT_ENTRY)); #endif local_irq_restore(flags);