From: Sowjanya Komatineni Date: Tue, 5 May 2020 02:31:55 +0000 (-0700) Subject: clk: tegra: Add Tegra210 CSI TPG clock gate X-Git-Tag: v5.10.7~2373^2~7^2^2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=dec396322d25ca5ce2f307b6da897060fdf9a782;p=platform%2Fkernel%2Flinux-rpi.git clk: tegra: Add Tegra210 CSI TPG clock gate Tegra210 CSI hardware internally uses PLLD for internal test pattern generator logic. PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD out to CSI during TPG mode. This patch adds this CSI TPG clock gate to Tegra210 clock driver to allow Tegra video driver to ungate CSI TPG clock during TPG mode and gate during non TPG mode. Acked-by: Stephen Boyd Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding --- diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index f2bb188..68cbb98 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3076,6 +3076,13 @@ static __init void tegra210_periph_clk_init(struct device_node *np, periph_clk_enb_refcnt); clks[TEGRA210_CLK_DSIB] = clk; + /* csi_tpg */ + clk = clk_register_gate(NULL, "csi_tpg", "pll_d", + CLK_SET_RATE_PARENT, clk_base + PLLD_BASE, + 23, 0, &pll_d_lock); + clk_register_clkdev(clk, "csi_tpg", NULL); + clks[TEGRA210_CLK_CSI_TPG] = clk; + /* la */ clk = tegra_clk_register_periph("la", la_parents, ARRAY_SIZE(la_parents), &tegra210_la, clk_base,