From: Faith Ekstrand Date: Mon, 14 Aug 2023 13:27:34 +0000 (-0500) Subject: intel/vec4: Stop passing around nir_dest X-Git-Tag: upstream/23.3.3~3347 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=de5bc9128c77a6d02371730cfd4a15ebf7654dfb;p=platform%2Fupstream%2Fmesa.git intel/vec4: Stop passing around nir_dest We want to get rid of nir_dest so back-ends need to stop storing it in structs and passing it through helpers. Reviewed-by: Kenneth Graunke Part-of: --- diff --git a/src/intel/compiler/brw_vec4.h b/src/intel/compiler/brw_vec4.h index cc99506..ca80338 100644 --- a/src/intel/compiler/brw_vec4.h +++ b/src/intel/compiler/brw_vec4.h @@ -309,9 +309,9 @@ public: virtual void nir_emit_undef(nir_undef_instr *instr); virtual void nir_emit_ssbo_atomic(int op, nir_intrinsic_instr *instr); - dst_reg get_nir_dest(const nir_dest &dest, enum brw_reg_type type); - dst_reg get_nir_dest(const nir_dest &dest, nir_alu_type type); - dst_reg get_nir_dest(const nir_dest &dest); + dst_reg get_nir_def(const nir_def &def, enum brw_reg_type type); + dst_reg get_nir_def(const nir_def &def, nir_alu_type type); + dst_reg get_nir_def(const nir_def &def); src_reg get_nir_src(const nir_src &src, enum brw_reg_type type, unsigned num_components = 4); src_reg get_nir_src(const nir_src &src, nir_alu_type type, diff --git a/src/intel/compiler/brw_vec4_gs_nir.cpp b/src/intel/compiler/brw_vec4_gs_nir.cpp index be05eb4..8ed94cb 100644 --- a/src/intel/compiler/brw_vec4_gs_nir.cpp +++ b/src/intel/compiler/brw_vec4_gs_nir.cpp @@ -50,7 +50,7 @@ vec4_gs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) type); src.swizzle = BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr)); - dest = get_nir_dest(instr->dest, src.type); + dest = get_nir_def(instr->dest.ssa, src.type); dest.writemask = brw_writemask_for_size(instr->num_components); emit(MOV(dest, src)); break; @@ -78,12 +78,12 @@ vec4_gs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) case nir_intrinsic_load_primitive_id: assert(gs_prog_data->include_primitive_id); - dest = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D); + dest = get_nir_def(instr->dest.ssa, BRW_REGISTER_TYPE_D); emit(MOV(dest, retype(brw_vec4_grf(1, 0), BRW_REGISTER_TYPE_D))); break; case nir_intrinsic_load_invocation_id: { - dest = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D); + dest = get_nir_def(instr->dest.ssa, BRW_REGISTER_TYPE_D); if (gs_prog_data->invocations > 1) emit(GS_OPCODE_GET_INSTANCE_ID, dest); else diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp index 10c0842..fdf71e5 100644 --- a/src/intel/compiler/brw_vec4_nir.cpp +++ b/src/intel/compiler/brw_vec4_nir.cpp @@ -183,15 +183,15 @@ dst_reg_for_nir_reg(vec4_visitor *v, nir_def *handle, } dst_reg -vec4_visitor::get_nir_dest(const nir_dest &dest) +vec4_visitor::get_nir_def(const nir_def &def) { - nir_intrinsic_instr *store_reg = nir_store_reg_for_def(&dest.ssa); + nir_intrinsic_instr *store_reg = nir_store_reg_for_def(&def); if (!store_reg) { dst_reg dst = - dst_reg(VGRF, alloc.allocate(DIV_ROUND_UP(dest.ssa.bit_size, 32))); - if (dest.ssa.bit_size == 64) + dst_reg(VGRF, alloc.allocate(DIV_ROUND_UP(def.bit_size, 32))); + if (def.bit_size == 64) dst.type = BRW_REGISTER_TYPE_DF; - nir_ssa_values[dest.ssa.index] = dst; + nir_ssa_values[def.index] = dst; return dst; } else { nir_src *indirect = @@ -207,15 +207,15 @@ vec4_visitor::get_nir_dest(const nir_dest &dest) } dst_reg -vec4_visitor::get_nir_dest(const nir_dest &dest, enum brw_reg_type type) +vec4_visitor::get_nir_def(const nir_def &def, enum brw_reg_type type) { - return retype(get_nir_dest(dest), type); + return retype(get_nir_def(def), type); } dst_reg -vec4_visitor::get_nir_dest(const nir_dest &dest, nir_alu_type type) +vec4_visitor::get_nir_def(const nir_def &def, nir_alu_type type) { - return get_nir_dest(dest, brw_type_for_nir_type(devinfo, type)); + return get_nir_def(def, brw_type_for_nir_type(devinfo, type)); } src_reg @@ -427,7 +427,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) /* We set EmitNoIndirectInput for VS */ unsigned load_offset = nir_src_as_uint(instr->src[0]); - dest = get_nir_dest(instr->dest); + dest = get_nir_def(instr->dest.ssa); src = src_reg(ATTR, nir_intrinsic_base(instr) + load_offset, glsl_type::uvec4_type); @@ -457,7 +457,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) unsigned ssbo_index = nir_src_is_const(instr->src[0]) ? nir_src_as_uint(instr->src[0]) : 0; - dst_reg result_dst = get_nir_dest(instr->dest); + dst_reg result_dst = get_nir_def(instr->dest.ssa); vec4_instruction *inst = new(mem_ctx) vec4_instruction(SHADER_OPCODE_GET_BUFFER_SIZE, result_dst); @@ -554,7 +554,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) src_reg read_result = emit_untyped_read(bld, surf_index, offset_reg, 1 /* dims */, 4 /* size*/, BRW_PREDICATE_NONE); - dst_reg dest = get_nir_dest(instr->dest); + dst_reg dest = get_nir_def(instr->dest.ssa); read_result.type = dest.type; read_result.swizzle = brw_swizzle_for_size(instr->num_components); emit(MOV(dest, read_result)); @@ -581,7 +581,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) /* Offsets are in bytes but they should always be multiples of 4 */ assert(nir_intrinsic_base(instr) % 4 == 0); - dest = get_nir_dest(instr->dest); + dest = get_nir_def(instr->dest.ssa); src = src_reg(dst_reg(UNIFORM, nir_intrinsic_base(instr) / 16)); src.type = dest.type; @@ -632,7 +632,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) case nir_intrinsic_load_ubo: { src_reg surf_index; - dest = get_nir_dest(instr->dest); + dest = get_nir_def(instr->dest.ssa); if (nir_src_is_const(instr->src[0])) { /* The block index is a constant, so just emit the binding table entry @@ -743,7 +743,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) const src_reg shader_clock = get_timestamp(); const enum brw_reg_type type = brw_type_for_base_type(glsl_type::uvec2_type); - dest = get_nir_dest(instr->dest, type); + dest = get_nir_def(instr->dest.ssa, type); emit(MOV(dest, shader_clock)); break; } @@ -758,7 +758,7 @@ vec4_visitor::nir_emit_ssbo_atomic(int op, nir_intrinsic_instr *instr) { dst_reg dest; if (nir_intrinsic_infos[instr->intrinsic].has_dest) - dest = get_nir_dest(instr->dest); + dest = get_nir_def(instr->dest.ssa); src_reg surface = get_nir_ssbo_intrinsic_index(instr); src_reg offset = get_nir_src(instr->src[1], 1); @@ -1083,7 +1083,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) nir_alu_type dst_type = (nir_alu_type) (nir_op_infos[instr->op].output_type | nir_dest_bit_size(instr->dest.dest)); - dst_reg dst = get_nir_dest(instr->dest.dest, dst_type); + dst_reg dst = get_nir_def(instr->dest.dest.ssa, dst_type); dst.writemask &= nir_component_mask(nir_dest_num_components(instr->dest.dest)); src_reg op[4]; @@ -1884,7 +1884,7 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) src_reg sample_index; src_reg mcs; - dst_reg dest = get_nir_dest(instr->dest, instr->dest_type); + dst_reg dest = get_nir_def(instr->dest.ssa, instr->dest_type); /* The hardware requires a LOD for buffer textures */ if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) diff --git a/src/intel/compiler/brw_vec4_tcs.cpp b/src/intel/compiler/brw_vec4_tcs.cpp index 32d146e..b132611 100644 --- a/src/intel/compiler/brw_vec4_tcs.cpp +++ b/src/intel/compiler/brw_vec4_tcs.cpp @@ -241,15 +241,15 @@ vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) { switch (instr->intrinsic) { case nir_intrinsic_load_invocation_id: - emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD), + emit(MOV(get_nir_def(instr->dest.ssa, BRW_REGISTER_TYPE_UD), invocation_id)); break; case nir_intrinsic_load_primitive_id: emit(TCS_OPCODE_GET_PRIMITIVE_ID, - get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD)); + get_nir_def(instr->dest.ssa, BRW_REGISTER_TYPE_UD)); break; case nir_intrinsic_load_patch_vertices_in: - emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D), + emit(MOV(get_nir_def(instr->dest.ssa, BRW_REGISTER_TYPE_D), brw_imm_d(key->input_vertices))); break; case nir_intrinsic_load_per_vertex_input: { @@ -261,7 +261,7 @@ vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) BRW_REGISTER_TYPE_UD); unsigned first_component = nir_intrinsic_component(instr); - dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D); + dst_reg dst = get_nir_def(instr->dest.ssa, BRW_REGISTER_TYPE_D); dst.writemask = brw_writemask_for_size(instr->num_components); emit_input_urb_read(dst, vertex_index, imm_offset, first_component, indirect_offset); @@ -275,7 +275,7 @@ vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) src_reg indirect_offset = get_indirect_offset(instr); unsigned imm_offset = nir_intrinsic_base(instr); - dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D); + dst_reg dst = get_nir_def(instr->dest.ssa, BRW_REGISTER_TYPE_D); dst.writemask = brw_writemask_for_size(instr->num_components); emit_output_urb_read(dst, imm_offset, nir_intrinsic_component(instr), diff --git a/src/intel/compiler/brw_vec4_tes.cpp b/src/intel/compiler/brw_vec4_tes.cpp index 7aef55d..6a2d03f 100644 --- a/src/intel/compiler/brw_vec4_tes.cpp +++ b/src/intel/compiler/brw_vec4_tes.cpp @@ -118,33 +118,33 @@ vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) switch (instr->intrinsic) { case nir_intrinsic_load_tess_coord: /* gl_TessCoord is part of the payload in g1 channels 0-2 and 4-6. */ - emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F), + emit(MOV(get_nir_def(instr->dest.ssa, BRW_REGISTER_TYPE_F), src_reg(brw_vec8_grf(1, 0)))); break; case nir_intrinsic_load_tess_level_outer: if (tes_prog_data->domain == BRW_TESS_DOMAIN_ISOLINE) { - emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F), + emit(MOV(get_nir_def(instr->dest.ssa, BRW_REGISTER_TYPE_F), swizzle(src_reg(ATTR, 1, glsl_type::vec4_type), BRW_SWIZZLE_ZWZW))); } else { - emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F), + emit(MOV(get_nir_def(instr->dest.ssa, BRW_REGISTER_TYPE_F), swizzle(src_reg(ATTR, 1, glsl_type::vec4_type), BRW_SWIZZLE_WZYX))); } break; case nir_intrinsic_load_tess_level_inner: if (tes_prog_data->domain == BRW_TESS_DOMAIN_QUAD) { - emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F), + emit(MOV(get_nir_def(instr->dest.ssa, BRW_REGISTER_TYPE_F), swizzle(src_reg(ATTR, 0, glsl_type::vec4_type), BRW_SWIZZLE_WZYX))); } else { - emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F), + emit(MOV(get_nir_def(instr->dest.ssa, BRW_REGISTER_TYPE_F), src_reg(ATTR, 1, glsl_type::float_type))); } break; case nir_intrinsic_load_primitive_id: emit(TES_OPCODE_GET_PRIMITIVE_ID, - get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD)); + get_nir_def(instr->dest.ssa, BRW_REGISTER_TYPE_UD)); break; case nir_intrinsic_load_input: @@ -178,7 +178,7 @@ vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) src_reg src = src_reg(ATTR, imm_offset, glsl_type::ivec4_type); src.swizzle = BRW_SWZ_COMP_INPUT(first_component); - emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D), src)); + emit(MOV(get_nir_def(instr->dest.ssa, BRW_REGISTER_TYPE_D), src)); prog_data->urb_read_length = MAX2(prog_data->urb_read_length, @@ -199,7 +199,7 @@ vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) /* Copy to target. We might end up with some funky writemasks landing * in here, but we really don't want them in the above pseudo-ops. */ - dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D); + dst_reg dst = get_nir_def(instr->dest.ssa, BRW_REGISTER_TYPE_D); dst.writemask = brw_writemask_for_size(instr->num_components); emit(MOV(dst, src)); break;