From: clyon Date: Wed, 21 Jan 2015 10:15:13 +0000 (+0000) Subject: [ARM/AArch64][testsuite] Add vqdmlal_n and vqdmlsl_n tests. X-Git-Tag: upstream/5.3.0~2396 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=de17cc7e85bbc4086b3c27576169e65d7d1ea828;p=platform%2Fupstream%2Flinaro-gcc.git [ARM/AArch64][testsuite] Add vqdmlal_n and vqdmlsl_n tests. 2015-01-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_n.inc: New file. * gcc.target/aarch64/advsimd-intrinsics/vqdmlal_n.c: New file. * gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_n.c: New file. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219932 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 23063a2..06e3138 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2015-01-21 Christophe Lyon + * gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_n.inc: New file. + * gcc.target/aarch64/advsimd-intrinsics/vqdmlal_n.c: New file. + * gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_n.c: New file. + +2015-01-21 Christophe Lyon + * gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_lane.inc: New file. * gcc.target/aarch64/advsimd-intrinsics/vqdmlal_lane.c: New file. * gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_lane.c: New file. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_n.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_n.inc new file mode 100644 index 0000000..fd885dd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_n.inc @@ -0,0 +1,59 @@ +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1(NAME) + +void FNNAME (INSN_NAME) (void) +{ + /* vector_res = vqdmlxl_n(vector, vector3, val), + then store the result. */ +#define TEST_VQDMLXL_N1(INSN, T1, T2, W, W2, N, V, EXPECTED_CUMULATIVE_SAT, CMT) \ + Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W, N)); \ + VECT_VAR(vector_res, T1, W, N) = \ + INSN##_##T2##W2(VECT_VAR(vector, T1, W, N), \ + VECT_VAR(vector3, T1, W2, N), \ + V); \ + vst1q_##T2##W(VECT_VAR(result, T1, W, N), \ + VECT_VAR(vector_res, T1, W, N)); \ + CHECK_CUMULATIVE_SAT(TEST_MSG, T1, W, N, EXPECTED_CUMULATIVE_SAT, CMT) + +#define TEST_VQDMLXL_N(INSN, T1, T2, W, W2, N, V, EXPECTED_CUMULATIVE_SAT, CMT) \ + TEST_VQDMLXL_N1(INSN, T1, T2, W, W2, N, V, EXPECTED_CUMULATIVE_SAT, CMT) + + DECL_VARIABLE(vector, int, 32, 4); + DECL_VARIABLE(vector3, int, 16, 4); + DECL_VARIABLE(vector_res, int, 32, 4); + + DECL_VARIABLE(vector, int, 64, 2); + DECL_VARIABLE(vector3, int, 32, 2); + DECL_VARIABLE(vector_res, int, 64, 2); + + clean_results (); + + VLOAD(vector, buffer, q, int, s, 32, 4); + VLOAD(vector, buffer, q, int, s, 64, 2); + + VDUP(vector3, , int, s, 16, 4, 0x55); + VDUP(vector3, , int, s, 32, 2, 0x55); + + /* Choose val arbitrarily. */ + TEST_VQDMLXL_N(INSN_NAME, int, s, 32, 16, 4, 0x22, expected_cumulative_sat, ""); + TEST_VQDMLXL_N(INSN_NAME, int, s, 64, 32, 2, 0x33, expected_cumulative_sat, ""); + + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, ""); + +#define TEST_MSG2 "(check mul cumulative saturation)" + VDUP(vector3, , int, s, 16, 4, 0x8000); + VDUP(vector3, , int, s, 32, 2, 0x80000000); + + TEST_VQDMLXL_N(INSN_NAME, int, s, 32, 16, 4, 0x8000, expected_cumulative_sat2, TEST_MSG2); + TEST_VQDMLXL_N(INSN_NAME, int, s, 64, 32, 2, 0x80000000, expected_cumulative_sat2, TEST_MSG2); + + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected2, TEST_MSG2); + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected2, TEST_MSG2); +} + +int main (void) +{ + FNNAME (INSN_NAME) (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal_n.c new file mode 100644 index 0000000..b84bca3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal_n.c @@ -0,0 +1,27 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define INSN_NAME vqdmlal_n +#define TEST_MSG "VQDMLAL_N" + +/* Expected values of cumulative_saturation flag. */ +int VECT_VAR(expected_cumulative_sat,int,32,4) = 0; +int VECT_VAR(expected_cumulative_sat,int,64,2) = 0; + +/* Expected results. */ +VECT_VAR_DECL(expected,int,32,4) [] = { 0x1684, 0x1685, 0x1686, 0x1687 }; +VECT_VAR_DECL(expected,int,64,2) [] = { 0x21ce, 0x21cf }; + +/* Expected values of cumulative_saturation flag when saturation + occurs. */ +int VECT_VAR(expected_cumulative_sat2,int,32,4) = 1; +int VECT_VAR(expected_cumulative_sat2,int,64,2) = 1; + +/* Expected results when saturation occurs. */ +VECT_VAR_DECL(expected2,int,32,4) [] = { 0x7fffffef, 0x7ffffff0, + 0x7ffffff1, 0x7ffffff2 }; +VECT_VAR_DECL(expected2,int,64,2) [] = { 0x7fffffffffffffef, + 0x7ffffffffffffff0 }; + +#include "vqdmlXl_n.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_n.c new file mode 100644 index 0000000..ff8d9d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_n.c @@ -0,0 +1,29 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define INSN_NAME vqdmlsl_n +#define TEST_MSG "VQDMLSL_N" + +/* Expected values of cumulative_saturation flag. */ +int VECT_VAR(expected_cumulative_sat,int,32,4) = 0; +int VECT_VAR(expected_cumulative_sat,int,64,2) = 0; + +/* Expected results. */ +VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffe95c, 0xffffe95d, + 0xffffe95e, 0xffffe95f }; +VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffde12, + 0xffffffffffffde13 }; + +/* Expected values of cumulative_saturation flag when saturation + occurs. */ +int VECT_VAR(expected_cumulative_sat2,int,32,4) = 1; +int VECT_VAR(expected_cumulative_sat2,int,64,2) = 1; + +/* Expected results when saturation occurs. */ +VECT_VAR_DECL(expected2,int,32,4) [] = { 0x80000000, 0x80000000, + 0x80000000, 0x80000000 }; +VECT_VAR_DECL(expected2,int,64,2) [] = { 0x8000000000000000, + 0x8000000000000000 }; + +#include "vqdmlXl_n.inc"