From: Will Deacon Date: Fri, 10 Mar 2017 20:32:24 +0000 (+0000) Subject: arm64: cache: Identify VPIPT I-caches X-Git-Tag: v4.14-rc1~917^2~71 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=dda288d7e4f605632dc6e19c69063f1725056208;p=platform%2Fkernel%2Flinux-rpi.git arm64: cache: Identify VPIPT I-caches Add support for detecting VPIPT I-caches, as introduced by ARMv8.2. Acked-by: Mark Rutland Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas --- diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index 7acb526..ea9bb4e 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -25,6 +25,7 @@ #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) +#define ICACHE_POLICY_VPIPT 0 #define ICACHE_POLICY_VIPT 2 #define ICACHE_POLICY_PIPT 3 @@ -45,6 +46,7 @@ #include #define ICACHEF_ALIASING 0 +#define ICACHEF_VPIPT 1 extern unsigned long __icache_flags; /* @@ -56,6 +58,11 @@ static inline int icache_is_aliasing(void) return test_bit(ICACHEF_ALIASING, &__icache_flags); } +static inline int icache_is_vpipt(void) +{ + return test_bit(ICACHEF_VPIPT, &__icache_flags); +} + static inline u32 cache_type_cwg(void) { return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 260b54f..7d27f4b 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -46,6 +46,7 @@ static char *icache_policy_str[] = { [0 ... ICACHE_POLICY_PIPT] = "RESERVED/UNKNOWN", [ICACHE_POLICY_VIPT] = "VIPT", [ICACHE_POLICY_PIPT] = "PIPT", + [ICACHE_POLICY_VPIPT] = "VPIPT", }; unsigned long __icache_flags; @@ -291,6 +292,9 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) switch (l1ip) { case ICACHE_POLICY_PIPT: break; + case ICACHE_POLICY_VPIPT: + set_bit(ICACHEF_VPIPT, &__icache_flags); + break; default: /* Fallthrough */ case ICACHE_POLICY_VIPT: