From: Monk Chiang Date: Thu, 13 Jul 2023 05:38:55 +0000 (+0800) Subject: RISC-V: Recognized zihintntl extensions X-Git-Tag: accepted/tizen/base/toolchain/20240202.060642~1 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=dbeb608cfd489e3be68d569eceacdc66fae5a93e;p=platform%2Fupstream%2Fgcc.git RISC-V: Recognized zihintntl extensions gcc/ChangeLog: * common/config/riscv/riscv-common.cc: (riscv_implied_info): Add zihintntl item. (riscv_ext_version_table): Ditto. (riscv_ext_flag_table): Ditto. * config/riscv/riscv-opts.h (MASK_ZIHINTNTL): New macro. (TARGET_ZIHINTNTL): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-22.c: New test. * gcc.target/riscv/predef-28.c: New test. (cherry-picked from commit ad0518d97cfc857183e524fabc104ebeec9e8ccd) Change-Id: Ibbce0e2b9ab9138fb218de9573b7173816e46f50 --- diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 2fc0f8b..24e9f1b 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -186,6 +186,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zksh", ISA_SPEC_CLASS_NONE, 1, 0}, {"zkt", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zihintntl", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0}, {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0}, {"zicbop",ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1223,6 +1225,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zksh", &gcc_options::x_riscv_zk_subext, MASK_ZKSH}, {"zkt", &gcc_options::x_riscv_zk_subext, MASK_ZKT}, + {"zihintntl", &gcc_options::x_riscv_zi_subext, MASK_ZIHINTNTL}, + {"zicboz", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOZ}, {"zicbom", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOM}, {"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP}, diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index cf0cd66..bd5d950 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -69,9 +69,11 @@ enum stack_protector_guard { #define MASK_ZICSR (1 << 0) #define MASK_ZIFENCEI (1 << 1) +#define MASK_ZIHINTNTL (1 << 2) #define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0) #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0) +#define TARGET_ZIHINTNTL ((riscv_zi_subext & MASK_ZIHINTNTL) != 0) #define MASK_ZAWRS (1 << 0) #define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0) diff --git a/gcc/testsuite/gcc.target/riscv/arch-22.c b/gcc/testsuite/gcc.target/riscv/arch-22.c new file mode 100644 index 0000000..cdc18e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-22.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zihintntl -mabi=lp64 -mcmodel=medlow" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/predef-28.c b/gcc/testsuite/gcc.target/riscv/predef-28.c new file mode 100644 index 0000000..81fdad5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-28.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zihintntl -mabi=lp64 -mcmodel=medlow" } */ + +int main () { + +#ifndef __riscv_arch_test +#error "__riscv_arch_test" +#endif + +#if __riscv_xlen != 64 +#error "__riscv_xlen" +#endif + +#if !defined(__riscv_i) +#error "__riscv_i" +#endif + +#if !defined(__riscv_c) +#error "__riscv_c" +#endif + +#if defined(__riscv_e) +#error "__riscv_e" +#endif + +#if !defined(__riscv_a) +#error "__riscv_a" +#endif + +#if !defined(__riscv_m) +#error "__riscv_m" +#endif + +#if !defined(__riscv_f) +#error "__riscv_f" +#endif + +#if !defined(__riscv_d) +#error "__riscv_d" +#endif + +#if !defined(__riscv_zihintntl) +#error "__riscv_zihintntl" +#endif + + return 0; +}