From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Date: Thu, 28 Jun 2018 16:28:00 +0000 (-0400)
Subject: drm/amd/display: add max scl ratio to soc bounding box
X-Git-Tag: v4.19~298^2~25^2~42
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=dbcac9c8abb117b11728da44fcaffcdc0d2fcc81;p=platform%2Fkernel%2Flinux-rpi.git

drm/amd/display: add max scl ratio to soc bounding box

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 6943801..c43d68b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -111,6 +111,8 @@ struct _vcs_dpi_soc_bounding_box_st {
 	double xfc_bus_transport_time_us;
 	double xfc_xbuf_latency_tolerance_us;
 	int use_urgent_burst_bw;
+	double max_hscl_ratio;
+	double max_vscl_ratio;
 	struct _vcs_dpi_voltage_scaling_st clock_limits[7];
 };