From: Thierry Reding Date: Thu, 18 Jun 2015 21:28:16 +0000 (-0400) Subject: clk: tegra: Update struct tegra_clk_pll_params kerneldoc X-Git-Tag: v4.14-rc1~4410^2~17^2~1 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=db592c4e2b6010069efc983ba3a35f0850844132;p=platform%2Fkernel%2Flinux-rpi.git clk: tegra: Update struct tegra_clk_pll_params kerneldoc Benson Leung pointed out that the kerneldoc for this structure has become stale. Update the field descriptions to match the structure content. Reported-by: Benson Leung Acked-by: Rhyland Klein Signed-off-by: Thierry Reding Reviewed-by: Benson Leung Signed-off-by: Rhyland Klein Signed-off-by: Thierry Reding --- diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 29799e7..bdc661c 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -157,7 +157,7 @@ struct div_nmp { }; /** - * struct clk_pll_params - PLL parameters + * struct tegra_clk_pll_params - PLL parameters * * @input_min: Minimum input frequency * @input_max: Maximum input frequency @@ -168,12 +168,24 @@ struct div_nmp { * @base_reg: PLL base reg offset * @misc_reg: PLL misc reg offset * @lock_reg: PLL lock reg offset - * @lock_bit_idx: Bit index for PLL lock status + * @lock_mask: Bitmask for PLL lock status * @lock_enable_bit_idx: Bit index to enable PLL lock + * @iddq_reg: PLL IDDQ register offset + * @iddq_bit_idx: Bit index to enable PLL IDDQ + * @aux_reg: AUX register offset + * @dyn_ramp_reg: Dynamic ramp control register offset + * @ext_misc_reg: Miscellaneous control register offsets + * @pmc_divnm_reg: n, m divider PMC override register offset (PLLM) + * @pmc_divp_reg: p divider PMC override register offset (PLLM) + * @flags: PLL flags + * @stepa_shift: Dynamic ramp step A field shift + * @stepb_shift: Dynamic ramp step B field shift * @lock_delay: Delay in us if PLL lock is not used + * @max_p: maximum value for the p divider + * @pdiv_tohw: mapping of p divider to register values + * @div_nmp: offsets and widths on n, m and p fields * @freq_table: array of frequencies supported by PLL * @fixed_rate: PLL rate if it is fixed - * @flags: PLL flags * * Flags: * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for