From: Xingyu Wu Date: Mon, 15 Aug 2022 07:05:05 +0000 (+0800) Subject: clk:starfive:Modify 'stg_apb' clock X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=db3fc924d7e25597d3160e51e7acf4020364f35a;p=platform%2Fkernel%2Flinux-starfive.git clk:starfive:Modify 'stg_apb' clock Change 'stg_apb' clock from external clock to internal clock. Signed-off-by: Xingyu Wu --- diff --git a/arch/riscv/boot/dts/starfive/jh7110-clk.dtsi b/arch/riscv/boot/dts/starfive/jh7110-clk.dtsi old mode 100644 new mode 100755 index 9c9aade..9461520 --- a/arch/riscv/boot/dts/starfive/jh7110-clk.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-clk.dtsi @@ -76,12 +76,6 @@ clock-frequency = <50000000>; }; - stg_apb: stg_apb { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <51200000>; - }; - gmac0_rmii_refin: gmac0_rmii_refin { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index e74f1d3..9efe2c8 100755 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -279,7 +279,7 @@ <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, <&tdm_ext>, <&mclk_ext>, <&jtag_tck_inner>, <&bist_apb>, - <&stg_apb>, <&clk_rtc>, + <&clk_rtc>, <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>; clock-names = "osc", "gmac1_rmii_refin", "gmac1_rgmii_rxin", @@ -287,7 +287,7 @@ "i2srx_bclk_ext", "i2srx_lrck_ext", "tdm_ext", "mclk_ext", "jtag_tck_inner", "bist_apb", - "stg_apb", "clk_rtc", + "clk_rtc", "gmac0_rmii_refin", "gmac0_rgmii_rxin"; #clock-cells = <1>; starfive,sys-syscon = <&sys_syscon 0x18 0x1c diff --git a/drivers/clk/starfive/clk-starfive-jh7110-stg.c b/drivers/clk/starfive/clk-starfive-jh7110-stg.c index 3105ba5..9ef47fe 100755 --- a/drivers/clk/starfive/clk-starfive-jh7110-stg.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-stg.c @@ -15,8 +15,6 @@ /* external clocks */ #define JH7110_OSC (JH7110_CLK_END + 0) -/* stg external clocks */ -#define JH7110_STG_APB (JH7110_CLK_END + 11) static const struct jh7110_clk_data jh7110_clk_stg_data[] __initconst = { //hifi4 @@ -127,6 +125,9 @@ int __init clk_starfive_jh7110_stg_init(struct platform_device *pdev, priv->pll[PLL_OF(JH7110_STG_SYSCON_PCLK)] = devm_clk_hw_register_fixed_factor(priv->dev, "u0_stg_syscon_pclk", "stg_apb", 0, 1, 1); + priv->pll[PLL_OF(JH7110_STG_APB)] = + devm_clk_hw_register_fixed_factor(priv->dev, + "stg_apb", "apb_bus", 0, 1, 1); for (idx = JH7110_CLK_SYS_REG_END; idx < JH7110_CLK_STG_REG_END; idx++) { u32 max = jh7110_clk_stg_data[idx].max; @@ -145,15 +146,13 @@ int __init clk_starfive_jh7110_stg_init(struct platform_device *pdev, for (i = 0; i < init.num_parents; i++) { unsigned int pidx = jh7110_clk_stg_data[idx].parents[i]; - if (pidx < JH7110_CLK_STG_REG_END) + if (pidx < JH7110_CLK_REG_END ) parents[i].hw = &priv->reg[pidx].hw; else if ((pidx < JH7110_CLK_STG_END) && - (pidx > JH7110_CLK_SYS_END)) + (pidx > (JH7110_CLK_SYS_END - 1))) parents[i].hw = priv->pll[PLL_OF(pidx)]; else if (pidx == JH7110_OSC) parents[i].fw_name = "osc"; - else if (pidx == JH7110_STG_APB) - parents[i].fw_name = "stg_apb"; } clk->hw.init = &init; diff --git a/include/dt-bindings/clock/starfive-jh7110-clkgen.h b/include/dt-bindings/clock/starfive-jh7110-clkgen.h index e565523..03ce495 100755 --- a/include/dt-bindings/clock/starfive-jh7110-clkgen.h +++ b/include/dt-bindings/clock/starfive-jh7110-clkgen.h @@ -350,24 +350,25 @@ #define JH7110_E2_IRQ_SYNC_CLK_CORE 324 #define JH7110_STG_CRG_PCLK 325 #define JH7110_STG_SYSCON_PCLK 326 +#define JH7110_STG_APB 327 -#define JH7110_CLK_STG_END 327 +#define JH7110_CLK_STG_END 328 /* aon other */ -#define JH7110_U0_GMAC5_CLK_PTP 327 -#define JH7110_U0_GMAC5_CLK_RMII 328 -#define JH7110_AON_SYSCON_PCLK 329 -#define JH7110_AON_IOMUX_PCLK 330 -#define JH7110_AON_CRG_PCLK 331 -#define JH7110_PMU_CLK_APB 332 -#define JH7110_PMU_CLK_WKUP 333 -#define JH7110_RTC_HMS_CLK_OSC32K_G 334 -#define JH7110_32K_OUT 335 -#define JH7110_RESET0_CTRL_CLK_SRC 336 +#define JH7110_U0_GMAC5_CLK_PTP 328 +#define JH7110_U0_GMAC5_CLK_RMII 329 +#define JH7110_AON_SYSCON_PCLK 330 +#define JH7110_AON_IOMUX_PCLK 331 +#define JH7110_AON_CRG_PCLK 332 +#define JH7110_PMU_CLK_APB 333 +#define JH7110_PMU_CLK_WKUP 334 +#define JH7110_RTC_HMS_CLK_OSC32K_G 335 +#define JH7110_32K_OUT 336 +#define JH7110_RESET0_CTRL_CLK_SRC 337 /* aon other and source */ -#define JH7110_PCLK_MUX_FUNC_PCLK 337 -#define JH7110_PCLK_MUX_BIST_PCLK 338 +#define JH7110_PCLK_MUX_FUNC_PCLK 338 +#define JH7110_PCLK_MUX_BIST_PCLK 339 -#define JH7110_CLK_END 339 +#define JH7110_CLK_END 340 #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */