From: Imre Deak <imre.deak@intel.com>
Date: Thu, 22 Dec 2011 20:48:28 +0000 (+0200)
Subject: gfx: imgv: fix parameter checking for exec cmd IOCTL
X-Git-Tag: 2.1b_release~398
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=da9a9697df7d77841726b1b4987883ec222d931c;p=kernel%2Fkernel-mfld-blackbay.git

gfx: imgv: fix parameter checking for exec cmd IOCTL

As the comment in code suggests the IOCTL accepts only flags specifying
a GPU read or write operation, for all other flags we should return
-EINVAL. The call to psb_ttm_bo_check_placement that would seemingly
check this is actually a no-op in this case. Replace it with an actual
check. While at it, also clean up the preceeding check.

This is also needed by an upcoming patch getting rid of
psb_ttm_bo_check_placement.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Pauli Nieminen <pauli.nieminen@linux.intel.com>
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
---

diff --git a/drivers/staging/mrst/drv/psb_sgx.c b/drivers/staging/mrst/drv/psb_sgx.c
index 8245e81..74c79a4 100644
--- a/drivers/staging/mrst/drv/psb_sgx.c
+++ b/drivers/staging/mrst/drv/psb_sgx.c
@@ -194,24 +194,18 @@ psb_placement_fence_type(struct ttm_buffer_object *bo,
 	*/
 	struct ttm_fence_object *old_fence;
 	uint32_t old_fence_type;
-	struct ttm_placement placement;
+	const uint64_t mask = PSB_GPU_ACCESS_READ | PSB_GPU_ACCESS_WRITE;
 
-	if (unlikely
-	    (!(set_val_flags &
-	       (PSB_GPU_ACCESS_READ | PSB_GPU_ACCESS_WRITE)))) {
-		DRM_ERROR
-		("GPU access type (read / write) is not indicated.\n");
+	if (!(set_val_flags & mask)) {
+		DRM_ERROR("GPU access type (read / write) is not indicated.\n");
 		return -EINVAL;
 	}
 
-	/* User space driver doesn't set any TTM placement flags in set_val_flags or clr_val_flags */
-	placement.num_placement = 0;/* FIXME  */
-	placement.num_busy_placement = 0;
-	placement.fpfn = 0;
-	placement.lpfn = 0;
-	ret = psb_ttm_bo_check_placement(bo, &placement);
-	if (unlikely(ret != 0))
-		return ret;
+	/* The only accepted bits are PSB_GPU_ACCES_{READ,WRITE}. */
+	if ((set_val_flags | clr_val_flags) & ~mask) {
+		DRM_ERROR("invalid set/clear flags\n");
+		return -EINVAL;
+	}
 
 	switch (new_fence_class) {
 	default: