From: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Thu, 30 Apr 2015 06:00:20 +0000 (-0400)
Subject: nvc0/ir: allow tess eval output loads to be CSE'd
X-Git-Tag: upstream/17.1.0~17465
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=da89e75d9c6399c8fb0286460c91a77778c0eec9;p=platform%2Fupstream%2Fmesa.git

nvc0/ir: allow tess eval output loads to be CSE'd

These only happen for gl_TessCoord which are constant.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
---

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index ad9bf6f..e9648aa 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -2518,6 +2518,8 @@ Instruction::isResultEqual(const Instruction *that) const
       case FILE_MEMORY_CONST:
       case FILE_SHADER_INPUT:
          return true;
+      case FILE_SHADER_OUTPUT:
+         return bb->getProgram()->getType() == Program::TYPE_TESSELLATION_EVAL;
       default:
          return false;
       }