From: H.J. Lu <hjl.tools@gmail.com>
Date: Tue, 24 Oct 2017 14:47:32 +0000 (-0700)
Subject: i386: Support .code64 directive only with 64-bit bfd
X-Git-Tag: users/ARM/embedded-binutils-master-2017q4~471
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=da5f19a2534936376228943de85fdd60f6ddd839;p=external%2Fbinutils.git

i386: Support .code64 directive only with 64-bit bfd

Without 64-bit bfd, we can't properly support .code64 directive in
32-bit mode.

	* config/tc-i386.c (md_pseudo_table): Add .code64 directive
	only if BFD64 is defined.
	* testsuite/gas/i386/code64-inval.l: New file.
	* gas/testsuite/gas/i386/code64-inval.s: Likewise.
	* gas/testsuite/gas/i386/code64.d: Likewise.
	* gas/testsuite/gas/i386/code64.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run mixed-mode-reloc32,
	att-regs, intel-regs, intel-expr and string-ok tests only if
	assembler supports x86-64.  Run code64 and code64-inval.
---

diff --git a/gas/ChangeLog b/gas/ChangeLog
index bb1aa01..138e43c 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,15 @@
+2017-10-24  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (md_pseudo_table): Add .code64 directive
+	only if BFD64 is defined.
+	* testsuite/gas/i386/code64-inval.l: New file.
+	* gas/testsuite/gas/i386/code64-inval.s: Likewise.
+	* gas/testsuite/gas/i386/code64.d: Likewise.
+	* gas/testsuite/gas/i386/code64.s: Likewise.
+	* testsuite/gas/i386/i386.exp: Run mixed-mode-reloc32,
+	att-regs, intel-regs, intel-expr and string-ok tests only if
+	assembler supports x86-64.  Run code64 and code64-inval.
+
 2017-10-23  Palmer Dabbelt  <palmer@dabbelt.com>
 
         * config/tc-riscv.c (riscv_frag_align_code): Align code by 4
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 5cde092..6b5026f 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1106,7 +1106,9 @@ const pseudo_typeS md_pseudo_table[] =
   {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
   {"code16", set_code_flag, CODE_16BIT},
   {"code32", set_code_flag, CODE_32BIT},
+#ifdef BFD64
   {"code64", set_code_flag, CODE_64BIT},
+#endif
   {"intel_syntax", set_intel_syntax, 1},
   {"att_syntax", set_intel_syntax, 0},
   {"intel_mnemonic", set_intel_mnemonic, 1},
diff --git a/gas/testsuite/gas/i386/code64-inval.l b/gas/testsuite/gas/i386/code64-inval.l
new file mode 100644
index 0000000..ea2e966
--- /dev/null
+++ b/gas/testsuite/gas/i386/code64-inval.l
@@ -0,0 +1,13 @@
+.*: Assembler messages:
+.*:3: Error: unknown pseudo-op: `.code64'
+.*:4: Error: `movabs' is only supported in 64-bit mode
+.*:5: Error: `movabs' is only supported in 64-bit mode
+GAS LISTING .*
+
+
+[ 	]*1[ 	]+\.include "code64\.s"
+[ 	]*1[ 	]+\.text
+[ 	]*2[ 	]+_start:
+[ 	]*3[ 	]+\.code64
+[ 	]*4[ 	]+movabs  0x87654321, %al
+[ 	]*5[ 	]+movabs  \$0x87654321, %rax
diff --git a/gas/testsuite/gas/i386/code64-inval.s b/gas/testsuite/gas/i386/code64-inval.s
new file mode 100644
index 0000000..ba5a377
--- /dev/null
+++ b/gas/testsuite/gas/i386/code64-inval.s
@@ -0,0 +1 @@
+.include "code64.s"
diff --git a/gas/testsuite/gas/i386/code64.d b/gas/testsuite/gas/i386/code64.d
new file mode 100644
index 0000000..684b44b
--- /dev/null
+++ b/gas/testsuite/gas/i386/code64.d
@@ -0,0 +1,11 @@
+#objdump: -dw -Mx86-64
+#name: .code64 directive in 32-bit mode.
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	a0 21 43 65 87 00 00 00 00 	movabs 0x87654321,%al
+ +[a-f0-9]+:	48 b8 21 43 65 87 00 00 00 00 	movabs \$0x87654321,%rax
+#pass
diff --git a/gas/testsuite/gas/i386/code64.s b/gas/testsuite/gas/i386/code64.s
new file mode 100644
index 0000000..8f2ded4
--- /dev/null
+++ b/gas/testsuite/gas/i386/code64.s
@@ -0,0 +1,5 @@
+	.text
+_start:
+	.code64
+	movabs  0x87654321, %al
+	movabs  $0x87654321, %rax
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index b6eb40a..1662d9c 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -458,10 +458,7 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
 	run_dump_test "bss"
 	run_dump_test "reloc32"
 	run_list_test "reloc32" "--defsym _bad_=1"
-	run_dump_test "mixed-mode-reloc32"
-	run_dump_test "att-regs"
 	run_dump_test "intel-got32"
-	run_dump_test "intel-regs"
 	run_dump_test "intel-movs32"
 	run_list_test "inval-equ-1" "-al"
 	run_list_test "inval-equ-2" "-al"
@@ -493,6 +490,15 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
 
 	run_dump_test "addend"
 
+	if { [gas_64_check] } then {
+	    run_dump_test "att-regs"
+	    run_dump_test "intel-regs"
+	    run_dump_test "mixed-mode-reloc32"
+	    run_dump_test "code64"
+	} else {
+	    run_list_test "code64-inval" "-I${srcdir}/$subdir -al"
+	}
+
 	if {![istarget "*-*-nacl*"]} then {
 	    run_dump_test "iamcu-1"
 	    run_dump_test "iamcu-2"
@@ -518,7 +524,7 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
 
 # Common tests
 if [expr [istarget "i*86-*-*"] || [istarget "x86_64-*-*"]] then {
-    if {![istarget "i*86-*-elfiamcu"]} then {
+    if {![istarget "i*86-*-elfiamcu"] && [gas_64_check]} then {
 	run_dump_test "intel-expr"
 	run_dump_test "string-ok"
     }