From: Clement Courbet <courbet@google.com>
Date: Wed, 2 May 2018 13:37:28 +0000 (+0000)
Subject: [MIPS] Fix DIV/DIVU scheduling classes.
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=da54914cde172a8e7a5c27a4be9e5e0772fca6cd;p=platform%2Fupstream%2Fllvm.git

[MIPS] Fix DIV/DIVU scheduling classes.

https://reviews.llvm.org/D46356.

llvm-svn: 331354
---

diff --git a/llvm/lib/Target/Mips/MipsScheduleGeneric.td b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
index 4087f1c..79c55db 100644
--- a/llvm/lib/Target/Mips/MipsScheduleGeneric.td
+++ b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
@@ -74,12 +74,12 @@ def : ItinRW<[GenericWriteMDUtoGPR], [II_MUL]>;
 def GenericWriteDIV : SchedWriteRes<[GenericIssueDIV]> {
   // Estimated worst case
   let Latency = 33;
-  let ResourceCycles = [1, 33];
+  let ResourceCycles = [33];
 }
 def GenericWriteDIVU : SchedWriteRes<[GenericIssueDIV]> {
   // Estimated worst case
   let Latency = 31;
-  let ResourceCycles = [1, 31];
+  let ResourceCycles = [31];
 }
 
 def : ItinRW<[GenericWriteDIV], [II_DIV]>;