From: Timur Kristóf <timur.kristof@gmail.com>
Date: Thu, 5 May 2022 19:51:44 +0000 (+0200)
Subject: radv/amdgpu: Pass new queue submit info structure to internal function.
X-Git-Tag: upstream/22.3.5~9191
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=da2ab1d8a2b1877aa7843e1f2afe14a2752c94b7;p=platform%2Fupstream%2Fmesa.git

radv/amdgpu: Pass new queue submit info structure to internal function.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16361>
---

diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index d32a8bd..2f21dd8 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -1314,27 +1314,28 @@ radv_amdgpu_cs_submit_zero(struct radv_amdgpu_ctx *ctx, enum amd_ip_type ip_type
 }
 
 static VkResult
-radv_amdgpu_winsys_cs_submit_internal(struct radeon_winsys_ctx *_ctx, enum amd_ip_type ip_type,
-                                      int queue_idx, struct radeon_cmdbuf **cs_array,
-                                      unsigned cs_count, struct radeon_cmdbuf *initial_preamble_cs,
-                                      struct radeon_cmdbuf *continue_preamble_cs,
+radv_amdgpu_winsys_cs_submit_internal(struct radeon_winsys_ctx *_ctx,
+                                      const struct radv_winsys_submit_info *submit,
                                       struct radv_winsys_sem_info *sem_info, bool can_patch)
 {
    struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
    VkResult result;
 
    assert(sem_info);
-   if (!cs_count) {
-      result = radv_amdgpu_cs_submit_zero(ctx, ip_type, queue_idx, sem_info);
-   } else if (!ring_can_use_ib_bos(ctx->ws, ip_type)) {
-      result = radv_amdgpu_winsys_cs_submit_sysmem(_ctx, queue_idx, sem_info, cs_array, cs_count,
-                                                   initial_preamble_cs, continue_preamble_cs);
+   if (!submit->cs_count) {
+      result = radv_amdgpu_cs_submit_zero(ctx, submit->ip_type, submit->queue_index, sem_info);
+   } else if (!ring_can_use_ib_bos(ctx->ws, submit->ip_type)) {
+      result = radv_amdgpu_winsys_cs_submit_sysmem(
+         _ctx, submit->queue_index, sem_info, submit->cs_array, submit->cs_count,
+         submit->initial_preamble_cs, submit->continue_preamble_cs);
    } else if (can_patch) {
-      result = radv_amdgpu_winsys_cs_submit_chained(_ctx, queue_idx, sem_info, cs_array, cs_count,
-                                                    initial_preamble_cs);
+      result =
+         radv_amdgpu_winsys_cs_submit_chained(_ctx, submit->queue_index, sem_info, submit->cs_array,
+                                              submit->cs_count, submit->initial_preamble_cs);
    } else {
-      result = radv_amdgpu_winsys_cs_submit_fallback(_ctx, queue_idx, sem_info, cs_array, cs_count,
-                                                     initial_preamble_cs);
+      result = radv_amdgpu_winsys_cs_submit_fallback(_ctx, submit->queue_index, sem_info,
+                                                     submit->cs_array, submit->cs_count,
+                                                     submit->initial_preamble_cs);
    }
 
    return result;
@@ -1411,10 +1412,7 @@ radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx, uint32_t submit_cou
    assert(submit_count);
 
    if (submit_count == 1) {
-      result = radv_amdgpu_winsys_cs_submit_internal(
-         _ctx, submits[0].ip_type, submits[0].queue_index, submits[0].cs_array,
-         submits[0].cs_count, submits[0].initial_preamble_cs, submits[0].continue_preamble_cs,
-         &sem_info, can_patch);
+      result = radv_amdgpu_winsys_cs_submit_internal(_ctx, &submits[0], &sem_info, can_patch);
    } else {
       unreachable("submitting to multiple queues at the same time is not supported yet.");
    }