From: Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
Date: Mon, 27 Sep 2010 13:36:48 +0000 (+0000)
Subject: 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
X-Git-Tag: sid-snapshot-20101001~47
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d9aee5d7f73be87d56ac14e0179afbd0dd59cb75;p=external%2Fbinutils.git

2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
	(main): Recognize the new CPU string.
	* s390-opc.c: Add new instruction formats and masks.
	* s390-opc.txt: Add new z196 instructions.

2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* opcode/s390.h: Add S390_OPCODE_Z196 to enum s390_opcode_cpu_val.

2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* config/tc-s390.c: (md_parse_option): New option -march=z196.
	* doc/c-s390.texi: Document new option.

2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* gas/s390/s390.exp: Run the zarch-z196 test.
	* gas/s390/zarch-z196.d: Add new instructions.
	* gas/s390/zarch-z196.s: Likewise.
	* gas/s390/zarch-z9-109.d: Likewise.
	* gas/s390/zarch-z9-109.s: Likewise.
---

diff --git a/gas/ChangeLog b/gas/ChangeLog
index b9d7363..55a2202 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
+
+	* config/tc-s390.c: (md_parse_option): New option -march=z196.
+	* doc/c-s390.texi: Document new option.
+
 2010-09-27  Tejas Belagod  <tejas.belagod@arm.com>
 
 	* config/tc-arm.c (do_neon_ldr_str): Deprecate ARM-mode PC-relative
diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c
index 0b49312..cf9f8a1 100644
--- a/gas/config/tc-s390.c
+++ b/gas/config/tc-s390.c
@@ -399,6 +399,8 @@ md_parse_option (int c, char *arg)
 	    current_cpu = S390_OPCODE_Z9_EC;
 	  else if (strcmp (arg + 5, "z10") == 0)
 	    current_cpu = S390_OPCODE_Z10;
+	  else if (strcmp (arg + 5, "z196") == 0)
+	    current_cpu = S390_OPCODE_Z196;
 	  else
 	    {
 	      as_bad (_("invalid switch -m%s"), arg);
diff --git a/gas/doc/c-s390.texi b/gas/doc/c-s390.texi
index 9408cb2..ab15312 100644
--- a/gas/doc/c-s390.texi
+++ b/gas/doc/c-s390.texi
@@ -17,7 +17,7 @@
 The s390 version of @code{@value{AS}} supports two architectures modes
 and seven chip levels. The architecture modes are the Enterprise System
 Architecture (ESA) and the newer z/Architecture mode. The chip levels
-are g5, g6, z900, z990, z9-109, z9-ec and z10.
+are g5, g6, z900, z990, z9-109, z9-ec, z10 and z196.
 
 @menu
 * s390 Options::                Command-line Options.
@@ -64,8 +64,9 @@ are recognized:
 @code{z900},
 @code{z990},
 @code{z9-109},
-@code{z9-ec} and
-@code{z10}.
+@code{z9-ec},
+@code{z10} and
+@code{z196}.
 Assembling an instruction that is not supported on the target processor
 results in an error message. Do not specify @code{g5} or @code{g6}
 with @samp{-mzarch}.
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 1fdb02d..3c8f2c5 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,5 +1,13 @@
 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 
+	* gas/s390/s390.exp: Run the zarch-z196 test.
+	* gas/s390/zarch-z196.d: Add new instructions.
+	* gas/s390/zarch-z196.s: Likewise.
+	* gas/s390/zarch-z9-109.d: Likewise.
+	* gas/s390/zarch-z9-109.s: Likewise.
+
+2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
+
 	* gas/s390/esa-g5.d: Adjust serveral instructions.
 	* gas/s390/esa-reloc.d: Likewise.
 	* gas/s390/esa-z990.d: Likewise.
diff --git a/gas/testsuite/gas/s390/s390.exp b/gas/testsuite/gas/s390/s390.exp
index fae071c..ec9805d 100644
--- a/gas/testsuite/gas/s390/s390.exp
+++ b/gas/testsuite/gas/s390/s390.exp
@@ -24,6 +24,7 @@ if [expr [istarget "s390-*-*"] ||  [istarget "s390x-*-*"]]  then {
     run_dump_test "zarch-z9-109" "{as -m64} {as -march=z9-109}"
     run_dump_test "zarch-z9-ec" "{as -m64} {as -march=z9-ec}"
     run_dump_test "zarch-z10" "{as -m64} {as -march=z10}"
+    run_dump_test "zarch-z196" "{as -m64} {as -march=z196}"
     run_dump_test "zarch-reloc" "{as -m64}"
     run_dump_test "zarch-operands" "{as -m64} {as -march=z9-109}"
 }
diff --git a/gas/testsuite/gas/s390/zarch-z196.d b/gas/testsuite/gas/s390/zarch-z196.d
new file mode 100644
index 0000000..a444cae
--- /dev/null
+++ b/gas/testsuite/gas/s390/zarch-z196.d
@@ -0,0 +1,255 @@
+#name: s390x opcode
+#objdump: -drw
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+.*:	b9 c8 80 67 [ 	]*ahhhr	%r6,%r7,%r8
+.*:	b9 d8 80 67 [ 	]*ahhlr	%r6,%r7,%r8
+.*:	cc 68 ff ff 02 18 [ 	]*aih	%r6,-65000
+.*:	b9 ca 80 67 [ 	]*alhhhr	%r6,%r7,%r8
+.*:	b9 da 80 67 [ 	]*alhhlr	%r6,%r7,%r8
+.*:	cc 6a 00 00 fd e8 [ 	]*alsih	%r6,65000
+.*:	cc 6b 00 00 fd e8 [ 	]*alsihn	%r6,65000
+.*:	cc 66 00 00 00 00 [ 	]*brcth	%r6,22 <foo\+0x22>
+.*:	b9 cd 00 67 [ 	]*chhr	%r6,%r7
+.*:	b9 dd 00 67 [ 	]*chlr	%r6,%r7
+.*:	e3 67 85 b3 01 cd [ 	]*chf	%r6,5555\(%r7,%r8\)
+.*:	cc 6d 00 00 fd e8 [ 	]*cih	%r6,65000
+.*:	b9 cf 00 67 [ 	]*clhhr	%r6,%r7
+.*:	b9 df 00 67 [ 	]*clhlr	%r6,%r7
+.*:	e3 67 85 b3 01 cf [ 	]*clhf	%r6,5555\(%r7,%r8\)
+.*:	cc 6f 00 09 eb 10 [ 	]*clih	%r6,650000
+.*:	e3 67 8a 4d fe c0 [ 	]*lbh	%r6,-5555\(%r7,%r8\)
+.*:	e3 67 8a 4d fe c4 [ 	]*lhh	%r6,-5555\(%r7,%r8\)
+.*:	e3 67 8a 4d fe ca [ 	]*lfh	%r6,-5555\(%r7,%r8\)
+.*:	e3 67 8a 4d fe c2 [ 	]*llch	%r6,-5555\(%r7,%r8\)
+.*:	e3 67 8a 4d fe c6 [ 	]*llhh	%r6,-5555\(%r7,%r8\)
+.*:	ec 67 0c 0d 0e 5d [ 	]*risbhg	%r6,%r7,12,13,14
+.*:	ec 67 0c 0d 0e 51 [ 	]*risblg	%r6,%r7,12,13,14
+.*:	e3 67 8a 4d fe c3 [ 	]*stch	%r6,-5555\(%r7,%r8\)
+.*:	e3 67 8a 4d fe c7 [ 	]*sthh	%r6,-5555\(%r7,%r8\)
+.*:	e3 67 8a 4d fe cb [ 	]*stfh	%r6,-5555\(%r7,%r8\)
+.*:	b9 c9 80 67 [ 	]*shhhr	%r6,%r7,%r8
+.*:	b9 d9 80 67 [ 	]*shhlr	%r6,%r7,%r8
+.*:	b9 cb 80 67 [ 	]*slhhhr	%r6,%r7,%r8
+.*:	b9 db 80 67 [ 	]*slhhlr	%r6,%r7,%r8
+.*:	eb 67 8a 4d fe f8 [ 	]*laa	%r6,%r7,-5555\(%r8\)
+.*:	eb 67 8a 4d fe e8 [ 	]*laag	%r6,%r7,-5555\(%r8\)
+.*:	eb 67 8a 4d fe fa [ 	]*laal	%r6,%r7,-5555\(%r8\)
+.*:	eb 67 8a 4d fe ea [ 	]*laalg	%r6,%r7,-5555\(%r8\)
+.*:	eb 67 8a 4d fe f4 [ 	]*lan	%r6,%r7,-5555\(%r8\)
+.*:	eb 67 8a 4d fe e4 [ 	]*lang	%r6,%r7,-5555\(%r8\)
+.*:	eb 67 8a 4d fe f7 [ 	]*lax	%r6,%r7,-5555\(%r8\)
+.*:	eb 67 8a 4d fe e7 [ 	]*laxg	%r6,%r7,-5555\(%r8\)
+.*:	eb 67 8a 4d fe f6 [ 	]*lao	%r6,%r7,-5555\(%r8\)
+.*:	eb 67 8a 4d fe e6 [ 	]*laog	%r6,%r7,-5555\(%r8\)
+.*:	c8 64 78 ae 84 57 [ 	]*lpd	%r6,2222\(%r7\),1111\(%r8\)
+.*:	c8 65 78 ae 84 57 [ 	]*lpdg	%r6,2222\(%r7\),1111\(%r8\)
+.*:	b9 f2 10 67 [ 	]*locro	%r6,%r7
+.*:	b9 f2 20 67 [ 	]*locrh	%r6,%r7
+.*:	b9 f2 20 67 [ 	]*locrh	%r6,%r7
+.*:	b9 f2 30 67 [ 	]*locrnle	%r6,%r7
+.*:	b9 f2 40 67 [ 	]*locrl	%r6,%r7
+.*:	b9 f2 40 67 [ 	]*locrl	%r6,%r7
+.*:	b9 f2 50 67 [ 	]*locrnhe	%r6,%r7
+.*:	b9 f2 60 67 [ 	]*locrlh	%r6,%r7
+.*:	b9 f2 70 67 [ 	]*locrne	%r6,%r7
+.*:	b9 f2 70 67 [ 	]*locrne	%r6,%r7
+.*:	b9 f2 80 67 [ 	]*locre	%r6,%r7
+.*:	b9 f2 80 67 [ 	]*locre	%r6,%r7
+.*:	b9 f2 90 67 [ 	]*locrnlh	%r6,%r7
+.*:	b9 f2 a0 67 [ 	]*locrhe	%r6,%r7
+.*:	b9 f2 b0 67 [ 	]*locrnl	%r6,%r7
+.*:	b9 f2 b0 67 [ 	]*locrnl	%r6,%r7
+.*:	b9 f2 c0 67 [ 	]*locrle	%r6,%r7
+.*:	b9 f2 d0 67 [ 	]*locrnh	%r6,%r7
+.*:	b9 f2 d0 67 [ 	]*locrnh	%r6,%r7
+.*:	b9 f2 e0 67 [ 	]*locrno	%r6,%r7
+.*:	b9 f2 80 67 [ 	]*locre	%r6,%r7
+.*:	b9 e2 10 67 [ 	]*locgro	%r6,%r7
+.*:	b9 e2 20 67 [ 	]*locgrh	%r6,%r7
+.*:	b9 e2 20 67 [ 	]*locgrh	%r6,%r7
+.*:	b9 e2 30 67 [ 	]*locgrnle	%r6,%r7
+.*:	b9 e2 40 67 [ 	]*locgrl	%r6,%r7
+.*:	b9 e2 40 67 [ 	]*locgrl	%r6,%r7
+.*:	b9 e2 50 67 [ 	]*locgrnhe	%r6,%r7
+.*:	b9 e2 60 67 [ 	]*locgrlh	%r6,%r7
+.*:	b9 e2 70 67 [ 	]*locgrne	%r6,%r7
+.*:	b9 e2 70 67 [ 	]*locgrne	%r6,%r7
+.*:	b9 e2 80 67 [ 	]*locgre	%r6,%r7
+.*:	b9 e2 80 67 [ 	]*locgre	%r6,%r7
+.*:	b9 e2 90 67 [ 	]*locgrnlh	%r6,%r7
+.*:	b9 e2 a0 67 [ 	]*locgrhe	%r6,%r7
+.*:	b9 e2 b0 67 [ 	]*locgrnl	%r6,%r7
+.*:	b9 e2 b0 67 [ 	]*locgrnl	%r6,%r7
+.*:	b9 e2 c0 67 [ 	]*locgrle	%r6,%r7
+.*:	b9 e2 d0 67 [ 	]*locgrnh	%r6,%r7
+.*:	b9 e2 d0 67 [ 	]*locgrnh	%r6,%r7
+.*:	b9 e2 e0 67 [ 	]*locgrno	%r6,%r7
+.*:	b9 e2 80 67 [ 	]*locgre	%r6,%r7
+.*:	eb 61 7a 4d fe f2 [ 	]*loc	%r6,-5555\(%r7\),1
+.*:	eb 62 7a 4d fe f2 [ 	]*loc	%r6,-5555\(%r7\),2
+.*:	eb 62 7a 4d fe f2 [ 	]*loc	%r6,-5555\(%r7\),2
+.*:	eb 63 7a 4d fe f2 [ 	]*loc	%r6,-5555\(%r7\),3
+.*:	eb 64 7a 4d fe f2 [ 	]*loc	%r6,-5555\(%r7\),4
+.*:	eb 64 7a 4d fe f2 [ 	]*loc	%r6,-5555\(%r7\),4
+.*:	eb 65 7a 4d fe f2 [ 	]*loc	%r6,-5555\(%r7\),5
+.*:	eb 66 7a 4d fe f2 [ 	]*loc	%r6,-5555\(%r7\),6
+.*:	eb 67 7a 4d fe f2 [ 	]*loc	%r6,-5555\(%r7\),7
+.*:	eb 67 7a 4d fe f2 [ 	]*loc	%r6,-5555\(%r7\),7
+.*:	eb 68 7a 4d fe f2 [ 	]*loc	%r6,-5555\(%r7\),8
+.*:	eb 68 7a 4d fe f2 [ 	]*loc	%r6,-5555\(%r7\),8
+.*:	eb 69 7a 4d fe f2 [ 	]*loc	%r6,-5555\(%r7\),9
+.*:	eb 6a 7a 4d fe f2 [ 	]*loc	%r6,-5555\(%r7\),10
+.*:	eb 6b 7a 4d fe f2 [ 	]*loc	%r6,-5555\(%r7\),11
+.*:	eb 6b 7a 4d fe f2 [ 	]*loc	%r6,-5555\(%r7\),11
+.*:	eb 6c 7a 4d fe f2 [ 	]*loc	%r6,-5555\(%r7\),12
+.*:	eb 6d 7a 4d fe f2 [ 	]*loc	%r6,-5555\(%r7\),13
+.*:	eb 6d 7a 4d fe f2 [ 	]*loc	%r6,-5555\(%r7\),13
+.*:	eb 6e 7a 4d fe f2 [ 	]*loc	%r6,-5555\(%r7\),14
+.*:	eb 68 7a 4d fe f2 [ 	]*loc	%r6,-5555\(%r7\),8
+.*:	eb 61 7a 4d fe e2 [ 	]*lgoc	%r6,-5555\(%r7\),1
+.*:	eb 62 7a 4d fe e2 [ 	]*lgoc	%r6,-5555\(%r7\),2
+.*:	eb 62 7a 4d fe e2 [ 	]*lgoc	%r6,-5555\(%r7\),2
+.*:	eb 63 7a 4d fe e2 [ 	]*lgoc	%r6,-5555\(%r7\),3
+.*:	eb 64 7a 4d fe e2 [ 	]*lgoc	%r6,-5555\(%r7\),4
+.*:	eb 64 7a 4d fe e2 [ 	]*lgoc	%r6,-5555\(%r7\),4
+.*:	eb 65 7a 4d fe e2 [ 	]*lgoc	%r6,-5555\(%r7\),5
+.*:	eb 66 7a 4d fe e2 [ 	]*lgoc	%r6,-5555\(%r7\),6
+.*:	eb 67 7a 4d fe e2 [ 	]*lgoc	%r6,-5555\(%r7\),7
+.*:	eb 67 7a 4d fe e2 [ 	]*lgoc	%r6,-5555\(%r7\),7
+.*:	eb 68 7a 4d fe e2 [ 	]*lgoc	%r6,-5555\(%r7\),8
+.*:	eb 68 7a 4d fe e2 [ 	]*lgoc	%r6,-5555\(%r7\),8
+.*:	eb 69 7a 4d fe e2 [ 	]*lgoc	%r6,-5555\(%r7\),9
+.*:	eb 6a 7a 4d fe e2 [ 	]*lgoc	%r6,-5555\(%r7\),10
+.*:	eb 6b 7a 4d fe e2 [ 	]*lgoc	%r6,-5555\(%r7\),11
+.*:	eb 6b 7a 4d fe e2 [ 	]*lgoc	%r6,-5555\(%r7\),11
+.*:	eb 6c 7a 4d fe e2 [ 	]*lgoc	%r6,-5555\(%r7\),12
+.*:	eb 6d 7a 4d fe e2 [ 	]*lgoc	%r6,-5555\(%r7\),13
+.*:	eb 6d 7a 4d fe e2 [ 	]*lgoc	%r6,-5555\(%r7\),13
+.*:	eb 6e 7a 4d fe e2 [ 	]*lgoc	%r6,-5555\(%r7\),14
+.*:	eb 68 7a 4d fe e2 [ 	]*lgoc	%r6,-5555\(%r7\),8
+.*:	eb 61 7a 4d fe f3 [ 	]*stoc	%r6,-5555\(%r7\),1
+.*:	eb 62 7a 4d fe f3 [ 	]*stoc	%r6,-5555\(%r7\),2
+.*:	eb 62 7a 4d fe f3 [ 	]*stoc	%r6,-5555\(%r7\),2
+.*:	eb 63 7a 4d fe f3 [ 	]*stoc	%r6,-5555\(%r7\),3
+.*:	eb 64 7a 4d fe f3 [ 	]*stoc	%r6,-5555\(%r7\),4
+.*:	eb 64 7a 4d fe f3 [ 	]*stoc	%r6,-5555\(%r7\),4
+.*:	eb 65 7a 4d fe f3 [ 	]*stoc	%r6,-5555\(%r7\),5
+.*:	eb 66 7a 4d fe f3 [ 	]*stoc	%r6,-5555\(%r7\),6
+.*:	eb 67 7a 4d fe f3 [ 	]*stoc	%r6,-5555\(%r7\),7
+.*:	eb 67 7a 4d fe f3 [ 	]*stoc	%r6,-5555\(%r7\),7
+.*:	eb 68 7a 4d fe f3 [ 	]*stoc	%r6,-5555\(%r7\),8
+.*:	eb 68 7a 4d fe f3 [ 	]*stoc	%r6,-5555\(%r7\),8
+.*:	eb 69 7a 4d fe f3 [ 	]*stoc	%r6,-5555\(%r7\),9
+.*:	eb 6a 7a 4d fe f3 [ 	]*stoc	%r6,-5555\(%r7\),10
+.*:	eb 6b 7a 4d fe f3 [ 	]*stoc	%r6,-5555\(%r7\),11
+.*:	eb 6b 7a 4d fe f3 [ 	]*stoc	%r6,-5555\(%r7\),11
+.*:	eb 6c 7a 4d fe f3 [ 	]*stoc	%r6,-5555\(%r7\),12
+.*:	eb 6d 7a 4d fe f3 [ 	]*stoc	%r6,-5555\(%r7\),13
+.*:	eb 6d 7a 4d fe f3 [ 	]*stoc	%r6,-5555\(%r7\),13
+.*:	eb 6e 7a 4d fe f3 [ 	]*stoc	%r6,-5555\(%r7\),14
+.*:	eb 68 7a 4d fe f3 [ 	]*stoc	%r6,-5555\(%r7\),8
+.*:	eb 61 7a 4d fe e3 [ 	]*stgoc	%r6,-5555\(%r7\),1
+.*:	eb 62 7a 4d fe e3 [ 	]*stgoc	%r6,-5555\(%r7\),2
+.*:	eb 62 7a 4d fe e3 [ 	]*stgoc	%r6,-5555\(%r7\),2
+.*:	eb 63 7a 4d fe e3 [ 	]*stgoc	%r6,-5555\(%r7\),3
+.*:	eb 64 7a 4d fe e3 [ 	]*stgoc	%r6,-5555\(%r7\),4
+.*:	eb 64 7a 4d fe e3 [ 	]*stgoc	%r6,-5555\(%r7\),4
+.*:	eb 65 7a 4d fe e3 [ 	]*stgoc	%r6,-5555\(%r7\),5
+.*:	eb 66 7a 4d fe e3 [ 	]*stgoc	%r6,-5555\(%r7\),6
+.*:	eb 67 7a 4d fe e3 [ 	]*stgoc	%r6,-5555\(%r7\),7
+.*:	eb 67 7a 4d fe e3 [ 	]*stgoc	%r6,-5555\(%r7\),7
+.*:	eb 68 7a 4d fe e3 [ 	]*stgoc	%r6,-5555\(%r7\),8
+.*:	eb 68 7a 4d fe e3 [ 	]*stgoc	%r6,-5555\(%r7\),8
+.*:	eb 69 7a 4d fe e3 [ 	]*stgoc	%r6,-5555\(%r7\),9
+.*:	eb 6a 7a 4d fe e3 [ 	]*stgoc	%r6,-5555\(%r7\),10
+.*:	eb 6b 7a 4d fe e3 [ 	]*stgoc	%r6,-5555\(%r7\),11
+.*:	eb 6b 7a 4d fe e3 [ 	]*stgoc	%r6,-5555\(%r7\),11
+.*:	eb 6c 7a 4d fe e3 [ 	]*stgoc	%r6,-5555\(%r7\),12
+.*:	eb 6d 7a 4d fe e3 [ 	]*stgoc	%r6,-5555\(%r7\),13
+.*:	eb 6d 7a 4d fe e3 [ 	]*stgoc	%r6,-5555\(%r7\),13
+.*:	eb 6e 7a 4d fe e3 [ 	]*stgoc	%r6,-5555\(%r7\),14
+.*:	eb 68 7a 4d fe e3 [ 	]*stgoc	%r6,-5555\(%r7\),8
+.*:	b9 f8 80 67 [ 	]*ark	%r6,%r7,%r8
+.*:	b9 e8 80 67 [ 	]*agrk	%r6,%r7,%r8
+.*:	ec 67 83 00 00 d8 [ 	]*ahik	%r6,%r7,-32000
+.*:	ec 67 83 00 00 d9 [ 	]*aghik	%r6,%r7,-32000
+.*:	b9 fa 80 67 [ 	]*alrk	%r6,%r7,%r8
+.*:	b9 ea 80 67 [ 	]*algrk	%r6,%r7,%r8
+.*:	ec 67 83 00 00 da [ 	]*alhsik	%r6,%r7,-32000
+.*:	ec 67 83 00 00 db [ 	]*alghsik	%r6,%r7,-32000
+.*:	b9 f4 80 67 [ 	]*nrk	%r6,%r7,%r8
+.*:	b9 e4 80 67 [ 	]*ngrk	%r6,%r7,%r8
+.*:	b9 f7 80 67 [ 	]*xrk	%r6,%r7,%r8
+.*:	b9 e7 80 67 [ 	]*xgrk	%r6,%r7,%r8
+.*:	b9 f6 80 67 [ 	]*ork	%r6,%r7,%r8
+.*:	b9 e6 80 67 [ 	]*ogrk	%r6,%r7,%r8
+.*:	eb 67 8a 4d fe dd [ 	]*slak	%r6,%r7,-5555\(%r8\)
+.*:	eb 67 8a 4d fe df [ 	]*sllk	%r6,%r7,-5555\(%r8\)
+.*:	eb 67 8a 4d fe dc [ 	]*srak	%r6,%r7,-5555\(%r8\)
+.*:	eb 67 8a 4d fe de [ 	]*srlk	%r6,%r7,-5555\(%r8\)
+.*:	b9 f9 80 67 [ 	]*srk	%r6,%r7,%r8
+.*:	b9 e9 80 67 [ 	]*sgrk	%r6,%r7,%r8
+.*:	b9 fb 80 67 [ 	]*slrk	%r6,%r7,%r8
+.*:	b9 eb 80 67 [ 	]*slgrk	%r6,%r7,%r8
+.*:	b9 e1 00 67 [ 	]*popcnt	%r6,%r7
+.*:	b9 ae 00 67 [ 	]*rrbm	%r6,%r7
+.*:	b3 94 37 59 [ 	]*cefbra	%f5,3,%r9,7
+.*:	b3 95 37 59 [ 	]*cdfbra	%f5,3,%r9,7
+.*:	b3 96 37 59 [ 	]*cxfbra	%f5,3,%r9,7
+.*:	b3 a4 37 59 [ 	]*cegbra	%f5,3,%r9,7
+.*:	b3 a5 37 59 [ 	]*cdgbra	%f5,3,%r9,7
+.*:	b3 a6 37 59 [ 	]*cxgbra	%f5,3,%r9,7
+.*:	b3 90 37 59 [ 	]*celfbr	%f5,3,%r9,7
+.*:	b3 91 37 59 [ 	]*cdlfbr	%f5,3,%r9,7
+.*:	b3 92 37 59 [ 	]*cxlfbr	%f5,3,%r9,7
+.*:	b3 a0 37 59 [ 	]*celgbr	%f5,3,%r9,7
+.*:	b3 a1 37 59 [ 	]*cdlgbr	%f5,3,%r9,7
+.*:	b3 a2 37 59 [ 	]*cxlgbr	%f5,3,%r9,7
+.*:	b3 98 37 59 [ 	]*cfebra	%r5,3,%f9,7
+.*:	b3 99 37 59 [ 	]*cfdbra	%r5,3,%f9,7
+.*:	b3 9a 37 59 [ 	]*cfxbra	%r5,3,%f9,7
+.*:	b3 a8 37 59 [ 	]*cgebra	%r5,3,%f9,7
+.*:	b3 a9 37 59 [ 	]*cgdbra	%r5,3,%f9,7
+.*:	b3 aa 37 59 [ 	]*cgxbra	%r5,3,%f9,7
+.*:	b3 9c 37 59 [ 	]*clfebr	%r5,3,%f9,7
+.*:	b3 9d 37 59 [ 	]*clfdbr	%r5,3,%f9,7
+.*:	b3 9e 37 59 [ 	]*clfxbr	%r5,3,%f9,7
+.*:	b3 ac 37 59 [ 	]*clgebr	%r5,3,%f9,7
+.*:	b3 ad 37 59 [ 	]*clgdbr	%r5,3,%f9,7
+.*:	b3 ae 37 59 [ 	]*clgxbr	%r5,3,%f9,7
+.*:	b3 57 37 59 [ 	]*fiebra	%f5,3,%f9,7
+.*:	b3 5f 37 59 [ 	]*fidbra	%f5,3,%f9,7
+.*:	b3 47 37 59 [ 	]*fixbra	%f5,3,%f9,7
+.*:	b3 44 37 59 [ 	]*ledbra	%f5,3,%f9,7
+.*:	b3 45 37 59 [ 	]*ldxbra	%f5,3,%f9,7
+.*:	b3 46 37 59 [ 	]*lexbra	%f5,3,%f9,7
+.*:	b3 d2 97 35 [ 	]*adtra	%f3,%f5,%f9,7
+.*:	b3 da 97 35 [ 	]*axtra	%f3,%f5,%f9,7
+.*:	b3 f1 37 59 [ 	]*cdgtra	%f5,3,%r9,7
+.*:	b9 51 37 59 [ 	]*cdftr	%f5,3,%r9,7
+.*:	b9 59 37 59 [ 	]*cxftr	%f5,3,%r9,7
+.*:	b3 f9 37 59 [ 	]*cxgtra	%f5,3,%r9,7
+.*:	b9 52 37 59 [ 	]*cdlgtr	%f5,3,%r9,7
+.*:	b9 5a 37 59 [ 	]*cxlgtr	%f5,3,%r9,7
+.*:	b9 53 37 59 [ 	]*cdlftr	%f5,3,%r9,7
+.*:	b9 5b 37 59 [ 	]*cxlftr	%f5,3,%r9,7
+.*:	b3 e1 37 59 [ 	]*cgdtra	%r5,3,%f9,7
+.*:	b3 e9 37 59 [ 	]*cgxtra	%r5,3,%f9,7
+.*:	b9 41 37 59 [ 	]*cfdtr	%r5,3,%f9,7
+.*:	b9 49 37 59 [ 	]*cfxtr	%r5,3,%f9,7
+.*:	b9 42 37 59 [ 	]*clgdtr	%r5,3,%f9,7
+.*:	b9 4a 37 59 [ 	]*clgxtr	%r5,3,%f9,7
+.*:	b9 43 37 59 [ 	]*clfdtr	%r5,3,%f9,7
+.*:	b9 4b 37 59 [ 	]*clfxtr	%r5,3,%f9,7
+.*:	b3 d1 97 35 [ 	]*ddtra	%f3,%f5,%f9,7
+.*:	b3 d9 97 35 [ 	]*dxtra	%f3,%f5,%f9,7
+.*:	b3 d0 97 35 [ 	]*mdtra	%f3,%f5,%f9,7
+.*:	b3 d8 97 35 [ 	]*mxtra	%f3,%f5,%f9,7
+.*:	b3 d3 97 35 [ 	]*sdtra	%f3,%f5,%f9,7
+.*:	b3 db 97 35 [ 	]*sxtra	%f3,%f5,%f9,7
+.*:	b2 b8 7f a0 [ 	]*srnmb	4000\(%r7\)
diff --git a/gas/testsuite/gas/s390/zarch-z196.s b/gas/testsuite/gas/s390/zarch-z196.s
new file mode 100644
index 0000000..0085819
--- /dev/null
+++ b/gas/testsuite/gas/s390/zarch-z196.s
@@ -0,0 +1,257 @@
+.text
+foo:
+	ahhhr	%r6,%r7,%r8
+	ahhlr	%r6,%r7,%r8
+	aih	%r6,-65000
+	alhhhr	%r6,%r7,%r8
+	alhhlr	%r6,%r7,%r8
+	alsih	%r6,65000
+	alsihn	%r6,65000
+	brcth	%r6,.
+	chhr	%r6,%r7
+	chlr	%r6,%r7
+	chf	%r6,5555(%r7,%r8)
+	cih	%r6,65000
+	clhhr	%r6,%r7
+	clhlr	%r6,%r7
+	clhf	%r6,5555(%r7,%r8)
+	clih	%r6,650000
+	lbh	%r6,-5555(%r7,%r8)
+	lhh	%r6,-5555(%r7,%r8)
+	lfh	%r6,-5555(%r7,%r8)
+	llch	%r6,-5555(%r7,%r8)
+	llhh	%r6,-5555(%r7,%r8)
+	risbhg	%r6,%r7,12,13,14
+	risblg	%r6,%r7,12,13,14
+	stch	%r6,-5555(%r7,%r8)
+	sthh	%r6,-5555(%r7,%r8)
+	stfh	%r6,-5555(%r7,%r8)
+	shhhr	%r6,%r7,%r8
+	shhlr	%r6,%r7,%r8
+	slhhhr	%r6,%r7,%r8
+	slhhlr	%r6,%r7,%r8
+	laa	%r6,%r7,-5555(%r8)
+	laag	%r6,%r7,-5555(%r8)
+	laal	%r6,%r7,-5555(%r8)
+	laalg	%r6,%r7,-5555(%r8)
+	lan	%r6,%r7,-5555(%r8)
+	lang	%r6,%r7,-5555(%r8)
+	lax	%r6,%r7,-5555(%r8)
+	laxg	%r6,%r7,-5555(%r8)
+	lao	%r6,%r7,-5555(%r8)
+	laog	%r6,%r7,-5555(%r8)
+	lpd	%r6,2222(%r7),1111(%r8)
+	lpdg	%r6,2222(%r7),1111(%r8)
+
+	locro	%r6,%r7
+	locrh	%r6,%r7
+	locrp	%r6,%r7
+	locrnle	%r6,%r7
+	locrl	%r6,%r7
+	locrm	%r6,%r7
+	locrnhe	%r6,%r7
+	locrlh	%r6,%r7
+	locrne	%r6,%r7
+	locrnz	%r6,%r7
+	locre	%r6,%r7
+	locrz	%r6,%r7
+	locrnlh	%r6,%r7
+	locrhe	%r6,%r7
+	locrnl	%r6,%r7
+	locrnm	%r6,%r7
+	locrle	%r6,%r7
+	locrnh	%r6,%r7
+	locrnp	%r6,%r7
+	locrno	%r6,%r7
+	locr	%r6,%r7,8
+
+	locgro	%r6,%r7
+	locgrh	%r6,%r7
+	locgrp	%r6,%r7
+	locgrnle %r6,%r7
+	locgrl	%r6,%r7
+	locgrm	%r6,%r7
+	locgrnhe %r6,%r7
+	locgrlh	%r6,%r7
+	locgrne	%r6,%r7
+	locgrnz	%r6,%r7
+	locgre	%r6,%r7
+	locgrz	%r6,%r7
+	locgrnlh %r6,%r7
+	locgrhe	%r6,%r7
+	locgrnl	%r6,%r7
+	locgrnm	%r6,%r7
+	locgrle	%r6,%r7
+	locgrnh	%r6,%r7
+	locgrnp	%r6,%r7
+	locgrno	%r6,%r7
+	locgr	%r6,%r7,8
+
+	loco	%r6,-5555(%r7)
+	loch	%r6,-5555(%r7)
+	locp	%r6,-5555(%r7)
+	locnle	%r6,-5555(%r7)
+	locl	%r6,-5555(%r7)
+	locm	%r6,-5555(%r7)
+	locnhe	%r6,-5555(%r7)
+	loclh	%r6,-5555(%r7)
+	locne	%r6,-5555(%r7)
+	locnz	%r6,-5555(%r7)
+	loce	%r6,-5555(%r7)
+	locz	%r6,-5555(%r7)
+	locnlh	%r6,-5555(%r7)
+	loche	%r6,-5555(%r7)
+	locnl	%r6,-5555(%r7)
+	locnm	%r6,-5555(%r7)
+	locle	%r6,-5555(%r7)
+	locnh	%r6,-5555(%r7)
+	locnp	%r6,-5555(%r7)
+	locno	%r6,-5555(%r7)
+	loc	%r6,-5555(%r7),8
+
+	lgoco	%r6,-5555(%r7)
+	lgoch	%r6,-5555(%r7)
+	lgocp	%r6,-5555(%r7)
+	lgocnle	%r6,-5555(%r7)
+	lgocl	%r6,-5555(%r7)
+	lgocm	%r6,-5555(%r7)
+	lgocnhe	%r6,-5555(%r7)
+	lgoclh	%r6,-5555(%r7)
+	lgocne	%r6,-5555(%r7)
+	lgocnz	%r6,-5555(%r7)
+	lgoce	%r6,-5555(%r7)
+	lgocz	%r6,-5555(%r7)
+	lgocnlh	%r6,-5555(%r7)
+	lgoche	%r6,-5555(%r7)
+	lgocnl	%r6,-5555(%r7)
+	lgocnm	%r6,-5555(%r7)
+	lgocle	%r6,-5555(%r7)
+	lgocnh	%r6,-5555(%r7)
+	lgocnp	%r6,-5555(%r7)
+	lgocno	%r6,-5555(%r7)
+	lgoc	%r6,-5555(%r7),8
+
+	stoco	%r6,-5555(%r7)
+	stoch	%r6,-5555(%r7)
+	stocp	%r6,-5555(%r7)
+	stocnle	%r6,-5555(%r7)
+	stocl	%r6,-5555(%r7)
+	stocm	%r6,-5555(%r7)
+	stocnhe	%r6,-5555(%r7)
+	stoclh	%r6,-5555(%r7)
+	stocne	%r6,-5555(%r7)
+	stocnz	%r6,-5555(%r7)
+	stoce	%r6,-5555(%r7)
+	stocz	%r6,-5555(%r7)
+	stocnlh	%r6,-5555(%r7)
+	stoche	%r6,-5555(%r7)
+	stocnl	%r6,-5555(%r7)
+	stocnm	%r6,-5555(%r7)
+	stocle	%r6,-5555(%r7)
+	stocnh	%r6,-5555(%r7)
+	stocnp	%r6,-5555(%r7)
+	stocno	%r6,-5555(%r7)
+	stoc	%r6,-5555(%r7),8
+
+	stgoco	%r6,-5555(%r7)
+	stgoch	%r6,-5555(%r7)
+	stgocp	%r6,-5555(%r7)
+	stgocnle %r6,-5555(%r7)
+	stgocl	%r6,-5555(%r7)
+	stgocm	%r6,-5555(%r7)
+	stgocnhe %r6,-5555(%r7)
+	stgoclh	%r6,-5555(%r7)
+	stgocne	%r6,-5555(%r7)
+	stgocnz	%r6,-5555(%r7)
+	stgoce	%r6,-5555(%r7)
+	stgocz	%r6,-5555(%r7)
+	stgocnlh %r6,-5555(%r7)
+	stgoche	%r6,-5555(%r7)
+	stgocnl	%r6,-5555(%r7)
+	stgocnm	%r6,-5555(%r7)
+	stgocle	%r6,-5555(%r7)
+	stgocnh	%r6,-5555(%r7)
+	stgocnp	%r6,-5555(%r7)
+	stgocno	%r6,-5555(%r7)
+	stgoc	%r6,-5555(%r7),8
+
+	ark	%r6,%r7,%r8
+	agrk	%r6,%r7,%r8
+	ahik	%r6,%r7,-32000
+	aghik	%r6,%r7,-32000
+	alrk	%r6,%r7,%r8
+	algrk	%r6,%r7,%r8
+	alhsik	%r6,%r7,-32000
+	alghsik	%r6,%r7,-32000
+	nrk	%r6,%r7,%r8
+	ngrk	%r6,%r7,%r8
+	xrk	%r6,%r7,%r8
+	xgrk	%r6,%r7,%r8
+	ork	%r6,%r7,%r8
+	ogrk	%r6,%r7,%r8
+	slak	%r6,%r7,-5555(%r8)
+	sllk	%r6,%r7,-5555(%r8)
+	srak	%r6,%r7,-5555(%r8)
+	srlk	%r6,%r7,-5555(%r8)
+	srk	%r6,%r7,%r8
+	sgrk	%r6,%r7,%r8
+	slrk	%r6,%r7,%r8
+	slgrk	%r6,%r7,%r8
+	popcnt	%r6,%r7
+	rrbm	%r6,%r7
+
+	cefbra %f5,3,%r9,7
+	cdfbra %f5,3,%r9,7
+	cxfbra %f5,3,%r9,7
+	cegbra %f5,3,%r9,7
+	cdgbra %f5,3,%r9,7
+	cxgbra %f5,3,%r9,7
+	celfbr %f5,3,%r9,7
+	cdlfbr %f5,3,%r9,7
+	cxlfbr %f5,3,%r9,7
+	celgbr %f5,3,%r9,7
+	cdlgbr %f5,3,%r9,7
+	cxlgbr %f5,3,%r9,7
+	cfebra %r5,3,%f9,7
+	cfdbra %r5,3,%f9,7
+	cfxbra %r5,3,%f9,7
+	cgebra %r5,3,%f9,7
+	cgdbra %r5,3,%f9,7
+	cgxbra %r5,3,%f9,7
+	clfebr %r5,3,%f9,7
+	clfdbr %r5,3,%f9,7
+	clfxbr %r5,3,%f9,7
+	clgebr %r5,3,%f9,7
+	clgdbr %r5,3,%f9,7
+	clgxbr %r5,3,%f9,7
+	fiebra %f5,3,%f9,7
+	fidbra %f5,3,%f9,7
+	fixbra %f5,3,%f9,7
+	ledbra %f5,3,%f9,7
+	ldxbra %f5,3,%f9,7
+	lexbra %f5,3,%f9,7
+	adtra %f3,%f5,%f9,7
+	axtra %f3,%f5,%f9,7
+	cdgtra %f5,3,%r9,7
+	cdftr %f5,3,%r9,7
+	cxftr %f5,3,%r9,7
+	cxgtra %f5,3,%r9,7
+	cdlgtr %f5,3,%r9,7
+	cxlgtr %f5,3,%r9,7
+	cdlftr %f5,3,%r9,7
+	cxlftr %f5,3,%r9,7
+	cgdtra %r5,3,%f9,7
+	cgxtra %r5,3,%f9,7
+	cfdtr %r5,3,%f9,7
+	cfxtr %r5,3,%f9,7
+	clgdtr %r5,3,%f9,7
+	clgxtr %r5,3,%f9,7
+	clfdtr %r5,3,%f9,7
+	clfxtr %r5,3,%f9,7
+	ddtra %f3,%f5,%f9,7
+	dxtra %f3,%f5,%f9,7
+	mdtra %f3,%f5,%f9,7
+	mxtra %f3,%f5,%f9,7
+	sdtra %f3,%f5,%f9,7
+	sxtra %f3,%f5,%f9,7
+	srnmb 4000(%r7)
diff --git a/gas/testsuite/gas/s390/zarch-z9-109.d b/gas/testsuite/gas/s390/zarch-z9-109.d
index 580a039..7c5797d 100644
--- a/gas/testsuite/gas/s390/zarch-z9-109.d
+++ b/gas/testsuite/gas/s390/zarch-z9-109.d
@@ -63,3 +63,6 @@ Disassembly of section .text:
 .*:	ed 95 af ff 60 3a [	 ]*may	%f6,%f9,4095\(%r5,%r10\)
 .*:	ed 95 af ff 60 3c [	 ]*mayh	%f6,%f9,4095\(%r5,%r10\)
 .*:	ed 95 af ff 60 38 [	 ]*mayl	%f6,%f9,4095\(%r5,%r10\)
+.*:	b9 eb 00 67 [	 ]*srstu	%r6,%r7
+.*:	d0 16 5f ff ad 05 [	 ]*trtr	4095\(23,%r5\),3333\(%r10\)
+.*:	07 07 [ 	]*nopr	%r7
\ No newline at end of file
diff --git a/gas/testsuite/gas/s390/zarch-z9-109.s b/gas/testsuite/gas/s390/zarch-z9-109.s
index 6caf3aa..35f1140 100644
--- a/gas/testsuite/gas/s390/zarch-z9-109.s
+++ b/gas/testsuite/gas/s390/zarch-z9-109.s
@@ -57,3 +57,5 @@ foo:
 	may	%f6,%f9,4095(%r5,%r10)
 	mayh	%f6,%f9,4095(%r5,%r10)
 	mayl	%f6,%f9,4095(%r5,%r10)
+	srstu	%r6,%r7
+	trtr	4095(23,%r5),3333(%r10)
diff --git a/include/ChangeLog b/include/ChangeLog
index fc00a55..97f3d44 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
+
+	* opcode/s390.h: Add S390_OPCODE_Z196 to enum s390_opcode_cpu_val.
+
 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
 	* arm.h (ARM_EXT_V6Z): Remove.
diff --git a/include/opcode/s390.h b/include/opcode/s390.h
index 33c0891..399904c 100644
--- a/include/opcode/s390.h
+++ b/include/opcode/s390.h
@@ -38,7 +38,8 @@ enum s390_opcode_cpu_val
     S390_OPCODE_Z990,
     S390_OPCODE_Z9_109,
     S390_OPCODE_Z9_EC,
-    S390_OPCODE_Z10
+    S390_OPCODE_Z10,
+    S390_OPCODE_Z196
   };
 
 /* The opcode table is an array of struct s390_opcode.  */
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 8a7b998..e219100 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,12 @@
 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 
+	* s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
+	(main): Recognize the new CPU string.
+	* s390-opc.c: Add new instruction formats and masks.
+	* s390-opc.txt: Add new z196 instructions.
+
+2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
+
 	* s390-dis.c (print_insn_s390): Pick instruction with most
 	specific mask.
 	* s390-opc.c: Add unused bits to the insn mask.
diff --git a/opcodes/s390-mkopc.c b/opcodes/s390-mkopc.c
index 1c1803e..84981cc 100644
--- a/opcodes/s390-mkopc.c
+++ b/opcodes/s390-mkopc.c
@@ -38,7 +38,8 @@ enum s390_opcode_cpu_val
     S390_OPCODE_Z990,
     S390_OPCODE_Z9_109,
     S390_OPCODE_Z9_EC,
-    S390_OPCODE_Z10
+    S390_OPCODE_Z10,
+    S390_OPCODE_Z196
   };
 
 struct op_struct
@@ -362,6 +363,8 @@ main (void)
 	    min_cpu = S390_OPCODE_Z9_EC;
 	  else if (strcmp (cpu_string, "z10") == 0)
 	    min_cpu = S390_OPCODE_Z10;
+	  else if (strcmp (cpu_string, "z196") == 0)
+	    min_cpu = S390_OPCODE_Z196;
 	  else {
 	    fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string);
 	    exit (1);
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 1a6628d..fea838e 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -178,7 +178,7 @@ const struct s390_operand s390_operands[] =
 
 /* Conditional mask operands.  */
 
-#define M_16   52                 /* 4 bit optional mask starting at 16 */
+#define M_16OPT   52              /* 4 bit optional mask starting at 16 */
   { 4, 16, S390_OPERAND_OPTIONAL },
 
 };
@@ -231,6 +231,7 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RIE_RRP    6, { R_8,R_12,J16_16,0,0,0 }          /* e.g. brxhg */
 #define INSTR_RIE_RRPU   6, { R_8,R_12,U4_32,J16_16,0,0 }      /* e.g. crj   */
 #define INSTR_RIE_RRP0   6, { R_8,R_12,J16_16,0,0,0 }          /* e.g. crjne */
+#define INSTR_RIE_RRI0   6, { R_8,R_12,I16_16,0,0,0 }          /* e.g. ahik  */
 #define INSTR_RIE_RUPI   6, { R_8,I8_32,U4_12,J16_16,0,0 }     /* e.g. cij   */
 #define INSTR_RIE_R0PI   6, { R_8,I8_32,J16_16,0,0,0 }         /* e.g. cijne */
 #define INSTR_RIE_RUPU   6, { R_8,U8_32,U4_12,J16_16,0,0 }     /* e.g. clij  */
@@ -272,16 +273,20 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RRF_F0FF2  4, { F_24,F_16,F_28,0,0,0 }           /* e.g. cpsdr */
 #define INSTR_RRF_F0FR   4, { F_24,F_16,R_28,0,0,0 }           /* e.g. iedtr */
 #define INSTR_RRF_FUFF   4, { F_24,F_16,F_28,U4_20,0,0 }       /* e.g. didbr */
+#define INSTR_RRF_FUFF2  4, { F_24,F_28,F_16,U4_20,0,0 }       /* e.g. adtra */
 #define INSTR_RRF_RURR   4, { R_24,R_28,R_16,U4_20,0,0 }       /* e.g. .insn */
 #define INSTR_RRF_R0RR   4, { R_24,R_16,R_28,0,0,0 }           /* e.g. idte  */
+#define INSTR_RRF_R0RR2  4, { R_24,R_28,R_16,0,0,0 }           /* e.g. ark   */
 #define INSTR_RRF_U0FF   4, { F_24,U4_16,F_28,0,0,0 }          /* e.g. fixr  */
 #define INSTR_RRF_U0RF   4, { R_24,U4_16,F_28,0,0,0 }          /* e.g. cfebr */
 #define INSTR_RRF_UUFF   4, { F_24,U4_16,F_28,U4_20,0,0 }      /* e.g. fidtr */
 #define INSTR_RRF_0UFF   4, { F_24,F_28,U4_20,0,0,0 }          /* e.g. ldetr */
 #define INSTR_RRF_FFRU   4, { F_24,F_16,R_28,U4_20,0,0 }       /* e.g. rrdtr */
-#define INSTR_RRF_M0RR   4, { R_24,R_28,M_16,0,0,0 }           /* e.g. sske  */
+#define INSTR_RRF_M0RR   4, { R_24,R_28,M_16OPT,0,0,0 }        /* e.g. sske  */
 #define INSTR_RRF_U0RR   4, { R_24,R_28,U4_16,0,0,0 }          /* e.g. clrt  */
 #define INSTR_RRF_00RR   4, { R_24,R_28,0,0,0,0 }              /* e.g. clrtne */
+#define INSTR_RRF_UUFR   4, { F_24,U4_16,R_28,U4_20,0,0 }      /* e.g. cdgtra */
+#define INSTR_RRF_UURF   4, { R_24,U4_16,F_28,U4_20,0,0 }      /* e.g. cgdtra */
 #define INSTR_RR_0R      2, { R_12, 0,0,0,0,0 }                /* e.g. br    */
 #define INSTR_RR_0R_OPT  2, { RO_12, 0,0,0,0,0 }               /* e.g. nopr  */
 #define INSTR_RR_FF      2, { F_8,F_12,0,0,0,0 }               /* e.g. adr   */
@@ -301,6 +306,8 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RSY_RURD   6, { R_8,U4_12,D20_20,B_16,0,0 }      /* e.g. icmh  */
 #define INSTR_RSY_AARD   6, { A_8,A_12,D20_20,B_16,0,0 }       /* e.g. lamy  */
 #define INSTR_RSY_CCRD   6, { C_8,C_12,D20_20,B_16,0,0 }       /* e.g. lamy  */
+#define INSTR_RSY_RDRM   6, { R_8,D20_20,B_16,U4_12,0,0 }      /* e.g. loc   */
+#define INSTR_RSY_RDR0   6, { R_8,D20_20,B_16,0,0,0 }          /* e.g. loc   */
 #define INSTR_RS_AARD    4, { A_8,A_12,D_20,B_16,0,0 }         /* e.g. lam   */
 #define INSTR_RS_CCRD    4, { C_8,C_12,D_20,B_16,0,0 }         /* e.g. lctl  */
 #define INSTR_RS_R0RD    4, { R_8,D_20,B_16,0,0,0 }            /* e.g. sll   */
@@ -332,6 +339,7 @@ const struct s390_operand s390_operands[] =
 #define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 }   /* e.g. plo   */
 #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 }   /* e.g. lmd   */
 #define INSTR_SSF_RRDRD  6, { D_20,B_16,D_36,B_32,R_8,0 }      /* e.g. mvcos */
+#define INSTR_SSF_RRDRD2 6, { R_8,D_20,B_16,D_36,B_32,0 }      /* e.g. lpd   */
 #define INSTR_S_00       4, { 0,0,0,0,0,0 }                    /* e.g. hsch  */
 #define INSTR_S_RD       4, { D_20,B_16,0,0,0,0 }              /* e.g. lpsw  */
 
@@ -339,6 +347,7 @@ const struct s390_operand s390_operands[] =
 #define MASK_RIE_RRP     { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RIE_RRPU    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RIE_RRP0    { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
+#define MASK_RIE_RRI0    { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
 #define MASK_RIE_RUPI    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RIE_R0PI    { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
 #define MASK_RIE_RUPU    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
@@ -378,8 +387,10 @@ const struct s390_operand s390_operands[] =
 #define MASK_RRF_F0FF2   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_F0FR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_FUFF    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RRF_FUFF2   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRF_RURR    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRF_R0RR    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RRF_R0RR2   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRF_U0FF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_U0RF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_UUFF    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
@@ -388,6 +399,8 @@ const struct s390_operand s390_operands[] =
 #define MASK_RRF_M0RR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_U0RR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_00RR    { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+#define MASK_RRF_UUFR    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RRF_UURF    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_0R       { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_0R_OPT   { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_FF       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
@@ -412,6 +425,8 @@ const struct s390_operand s390_operands[] =
 #define MASK_RSY_RURD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RSY_AARD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RSY_CCRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RSY_RDRM    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RSY_RDR0    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RXE_FRRD    { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
 #define MASK_RXE_RRRD    { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
 #define MASK_RXF_FRRDF   { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
@@ -438,6 +453,7 @@ const struct s390_operand s390_operands[] =
 #define MASK_SS_RRRDRD2  { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_SS_RRRDRD3  { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_SSF_RRDRD   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SSF_RRDRD2  { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_S_00        { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
 #define MASK_S_RD        { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index 36a2d03..9393ba4 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -419,7 +419,7 @@ e3000000000e cvbg RXE_RRRD "convert to binary 64" z900 zarch
 e30000000024 stg RXE_RRRD "store 64" z900 zarch
 e30000000080 ng RXE_RRRD "and 64" z900 zarch
 e30000000021 clg RXE_RRRD "compare logical 64" z900 zarch
-e30000000031 clgf RXE_RRRD "comparee logical 64<32" z900 zarch
+e30000000031 clgf RXE_RRRD "compare logical 64<32" z900 zarch
 e30000000081 og RXE_RRRD "or 64" z900 zarch
 e30000000082 xg RXE_RRRD "exclusive or 64" z900 zarch
 e30000000004 lg RXE_RRRD "load 64" z900 zarch
@@ -776,6 +776,8 @@ b9b2 cu41 RRE_RR "convert utf-32 to utf-8" z9-109 zarch
 b2a7 cu12 RRF_M0RR "convert utf-8 to utf-16" z9-109 zarch
 b2a7 cutfu RRF_M0RR "convert utf-8 to unicode" z9-109 zarch
 b9b0 cu14 RRF_M0RR "convert utf-8 to utf-32" z9-109 zarch
+b9eb srstu RRE_RR "search string unicode" z9-109 zarch
+d0 trtr SS_L0RDRD "tranlate and test reverse" z9-109 zarch
 # z9-109 unnormalized hfp multiply & multiply and add
 b33b myr RRF_F0FF "multiply unnormalized long hfp" z9-109 zarch
 b33d myhr RRF_F0FF "multiply unnormalized long hfp high" z9-109 zarch
@@ -958,3 +960,136 @@ b9a2 ptf RRE_R0 "perform topology function" z10 zarch
 b9af pfmf RRE_RR "perform frame management function" z10 zarch
 b9bf trte RRF_M0RR "translate and test extended" z10 zarch
 b9bd trtre RRF_M0RR "translate and test reverse extended" z10 zarch
+b9c8 ahhhr RRF_R0RR2 "add high high" z196 zarch
+b9d8 ahhlr RRF_R0RR2 "add high low" z196 zarch
+cc08 aih RIL_RI "add immediate high" z196 zarch
+b9ca alhhhr RRF_R0RR2 "add logical high high" z196 zarch
+b9da alhhlr RRF_R0RR2 "add logical high low" z196 zarch
+cc0a alsih RIL_RI "add logical with signed immediate high with cc" z196 zarch
+cc0b alsihn RIL_RI "add logical with signed immediate high no cc" z196 zarch
+cc06 brcth RIL_RP "branch relative on count high" z196 zarch
+b9cd chhr RRE_RR "compare high high" z196 zarch
+b9dd chlr RRE_RR "compare high low" z196 zarch
+e300000000cd chf RXY_RRRD "compare high" z196 zarch
+cc0d cih RIL_RI "compare immediate high" z196 zarch
+b9cf clhhr RRE_RR "compare logical high high" z196 zarch
+b9df clhlr RRE_RR "compare logical high low" z196 zarch
+e300000000cf clhf RXY_RRRD "compare logical high" z196 zarch
+cc0f clih RIL_RI "compare logical immediate" z196 zarch
+e300000000c0 lbh RXY_RRRD "load byte high" z196 zarch
+e300000000c4 lhh RXY_RRRD "load halfword high" z196 zarch
+e300000000ca lfh RXY_RRRD "load high" z196 zarch
+e300000000c2 llch RXY_RRRD "load logical character high" z196 zarch
+e300000000c6 llhh RXY_RRRD "load logical halfword high" z196 zarch
+ec000000005D risbhg RIE_RRUUU "rotate then insert selected bits high" z196 zarch
+ec0000000051 risblg RIE_RRUUU "rotate then insert selected bits low" z196 zarch
+e300000000c3 stch RXY_RRRD "store character high" z196 zarch
+e300000000c7 sthh RXY_RRRD "store halfword high" z196 zarch
+e300000000cb stfh RXY_RRRD "store high" z196 zarch
+b9c9 shhhr RRF_R0RR2 "subtract high high" z196 zarch
+b9d9 shhlr RRF_R0RR2 "subtract high low" z196 zarch
+b9cb slhhhr RRF_R0RR2 "subtract logical high high" z196 zarch
+b9db slhhlr RRF_R0RR2 "subtract logical high low" z196 zarch
+eb00000000f8 laa RSY_RRRD "load and add 32 bit" z196 zarch
+eb00000000e8 laag RSY_RRRD "load and add 64 bit" z196 zarch
+eb00000000fa laal RSY_RRRD "load and add logical 32 bit" z196 zarch
+eb00000000ea laalg RSY_RRRD "load and add logical 64 bit" z196 zarch
+eb00000000f4 lan RSY_RRRD "load and and 32 bit" z196 zarch
+eb00000000e4 lang RSY_RRRD "load and and 64 bit" z196 zarch
+eb00000000f7 lax RSY_RRRD "load and exclusive or 32 bit" z196 zarch
+eb00000000e7 laxg RSY_RRRD "load and exclusive or 64 bit" z196 zarch
+eb00000000f6 lao RSY_RRRD "load and or 32 bit" z196 zarch
+eb00000000e6 laog RSY_RRRD "load and or 64 bit" z196 zarch
+c804 lpd SSF_RRDRD2 "load pair disjoint 32 bit" z196 zarch
+c805 lpdg SSF_RRDRD2 "load pair disjoint 64 bit" z196 zarch
+b9f2 locr RRF_U0RR "load on condition 32 bit" z196 zarch
+b9f200000000 locr*16 RRF_00RR "load on condition 32 bit" z196 zarch
+b9e2 locgr RRF_U0RR "load on condition 64  bit" z196 zarch
+b9e200000000 locgr*16 RRF_00RR "load on condition 64  bit" z196 zarch
+eb00000000f2 loc RSY_RDRM "load on condition 32 bit" z196 zarch
+eb00000000f2 loc*12 RSY_RDR0 "load on condition 32 bit" z196 zarch
+eb00000000e2 lgoc RSY_RDRM "load on condition 64 bit" z196 zarch
+eb00000000e2 lgoc*12 RSY_RDR0 "load on condition 64 bit" z196 zarch
+eb00000000f3 stoc RSY_RDRM "store on condition 32 bit" z196 zarch
+eb00000000f3 stoc*12 RSY_RDR0 "store on condition 32 bit" z196 zarch
+eb00000000e3 stgoc RSY_RDRM "store on condition 64 bit" z196 zarch
+eb00000000e3 stgoc*12 RSY_RDR0 "store on condition 64 bit" z196 zarch
+b9f8 ark RRF_R0RR2 "add 3 operands 32 bit" z196 zarch
+b9e8 agrk RRF_R0RR2 "add 3 operands 64 bit" z196 zarch
+ec00000000d8 ahik RIE_RRI0 "add immediate 3 operands 32 bit" z196 zarch
+ec00000000d9 aghik RIE_RRI0 "add immediate 3 operands 64 bit" z196 zarch
+b9fa alrk RRF_R0RR2 "add logical 3 operands 32 bit" z196 zarch
+b9ea algrk RRF_R0RR2 "add logical 3 operands 64 bit" z196 zarch
+ec00000000da alhsik RIE_RRI0 "add logical immediate 3 operands 32 bit" z196 zarch
+ec00000000db alghsik RIE_RRI0 "add logical immediate 3 operands 64 bit" z196 zarch
+b9f4 nrk RRF_R0RR2 "and 3 operands 32 bit" z196 zarch
+b9e4 ngrk RRF_R0RR2 "and 3 operands 64 bit" z196 zarch
+b9f7 xrk RRF_R0RR2 "xor 3 operands 32 bit" z196 zarch
+b9e7 xgrk RRF_R0RR2 "xor 3 operands 64 bit" z196 zarch
+b9f6 ork RRF_R0RR2 "or 3 operands 32 bit" z196 zarch
+b9e6 ogrk RRF_R0RR2 "or 3 operands 64 bit" z196 zarch
+eb00000000dd slak RSY_RRRD "shift left single 3 operands 32 bit" z196 zarch
+eb00000000df sllk RSY_RRRD "shift left single logical 3 operands 32 bit" z196 zarch
+eb00000000dc srak RSY_RRRD "shift right single 3 operands 32 bit" z196 zarch
+eb00000000de srlk RSY_RRRD "shift right single logical 3 operands 32 bit" z196 zarch
+b9f9 srk RRF_R0RR2 "subtract 3 operands 32 bit" z196 zarch
+b9e9 sgrk RRF_R0RR2 "subtract 3 operands 64 bit" z196 zarch
+b9fb slrk RRF_R0RR2 "subtract logical 3 operands 32 bit" z196 zarch
+b9eb slgrk RRF_R0RR2 "subtract logical 3 operands 64 bit" z196 zarch
+b9e1 popcnt RRE_RR "population count" z196 zarch
+b9ae rrbm RRE_RR "reset reference bits multiple" z196 zarch
+b394 cefbra RRF_UUFR "convert from 32 bit fixed to short bfp with rounding mode" z196 zarch
+b395 cdfbra RRF_UUFR "convert from 32 bit fixed to long bfp with rounding mode" z196 zarch
+b396 cxfbra RRF_UUFR "convert from 32 bit fixed to extended bfp with rounding mode" z196 zarch
+b3a4 cegbra RRF_UUFR "convert from 64 bit fixed to short bfp with rounding mode" z196 zarch
+b3a5 cdgbra RRF_UUFR "convert from 64 bit fixed to long bfp with rounding mode" z196 zarch
+b3a6 cxgbra RRF_UUFR "convert from 64 bit fixed to extended bfp with rounding mode" z196 zarch
+b390 celfbr RRF_UUFR "convert from 32 bit logical fixed to short bfp with rounding mode" z196 zarch
+b391 cdlfbr RRF_UUFR "convert from 32 bit logical fixed to long bfp with rounding mode" z196 zarch
+b392 cxlfbr RRF_UUFR "convert from 32 bit logical fixed to extended bfp with rounding mode" z196 zarch
+b3a0 celgbr RRF_UUFR "convert from 64 bit logical fixed to short bfp with rounding mode" z196 zarch
+b3a1 cdlgbr RRF_UUFR "convert from 64 bit logical fixed to long bfp with rounding mode" z196 zarch
+b3a2 cxlgbr RRF_UUFR "convert from 64 bit logical fixed to extended bfp with rounding mode" z196 zarch
+b398 cfebra RRF_UURF "convert to 32 bit fixed from short bfp with rounding mode" z196 zarch
+b399 cfdbra RRF_UURF "convert to 32 bit fixed from long bfp with rounding mode" z196 zarch
+b39a cfxbra RRF_UURF "convert to 32 bit fixed from extended bfp with rounding mode" z196 zarch
+b3a8 cgebra RRF_UURF "convert to 64 bit fixed from short bfp with rounding mode" z196 zarch
+b3a9 cgdbra RRF_UURF "convert to 64 bit fixed from long bfp with rounding mode" z196 zarch
+b3aa cgxbra RRF_UURF "convert to 64 bit fixed from extended bfp with rounding mode" z196 zarch
+b39c clfebr RRF_UURF "convert to 32 bit fixed logical from short bfp with rounding mode" z196 zarch
+b39d clfdbr RRF_UURF "convert to 32 bit fixed logical from long bfp with rounding mode" z196 zarch
+b39e clfxbr RRF_UURF "convert to 32 bit fixed logical from extended bfp with rounding mode" z196 zarch
+b3ac clgebr RRF_UURF "convert to 64 bit fixed logical from short bfp with rounding mode" z196 zarch
+b3ad clgdbr RRF_UURF "convert to 64 bit fixed logical from long bfp with rounding mode" z196 zarch
+b3ae clgxbr RRF_UURF "convert to 64 bit fixed logical from extended bfp with rounding mode" z196 zarch
+b357 fiebra RRF_UUFF "load fp integer short bfp with rounding mode" z196 zarch
+b35f fidbra RRF_UUFF "load fp integer long bfp with rounding mode" z196 zarch
+b347 fixbra RRF_UUFF "load fp integer extended bfp with rounding mode" z196 zarch
+b344 ledbra RRF_UUFF "load rounded short/long bfp to short/long bfp with rounding mode" z196 zarch
+b345 ldxbra RRF_UUFF "load rounded long/extended bfp to long/extended bfp with rounding mode" z196 zarch
+b346 lexbra RRF_UUFF "load rounded short/extended bfp to short/extended bfp with rounding mode" z196 zarch
+b3d2 adtra RRF_FUFF2 "add long dfp with rounding mode" z196 zarch
+b3da axtra RRF_FUFF2 "add extended dfp with rounding mode" z196 zarch
+b3f1 cdgtra RRF_UUFR "convert from fixed long dfp with rounding mode" z196 zarch
+b951 cdftr RRF_UUFR "convert from 32 bit fixed to long dfp with rounding mode" z196 zarch
+b959 cxftr RRF_UUFR "convert from 32 bit fixed to extended dfp with rounding mode" z196 zarch
+b3f9 cxgtra RRF_UUFR "convert from fixed extended dfp with rounding mode" z196 zarch
+b952 cdlgtr RRF_UUFR "convert from 64 bit fixed logical to long dfp with rounding mode" z196 zarch
+b95a cxlgtr RRF_UUFR "convert from 64 bit fixed logical to extended dfp with rounding mode" z196 zarch
+b953 cdlftr RRF_UUFR "convert from 32 bit fixed logical to long dfp with rounding mode" z196 zarch
+b95b cxlftr RRF_UUFR "convert from 32 bit fixed logical to extended dfp with rounding mode" z196 zarch
+b3e1 cgdtra RRF_UURF "convert to 64 bit fixed from long dfp with rounding mode" z196 zarch
+b3e9 cgxtra RRF_UURF "convert to 64 bit fixed from extended dfp with rounding mode" z196 zarch
+b941 cfdtr RRF_UURF "convert to 32 bit fixed from long dfp source with rounding mode" z196 zarch
+b949 cfxtr RRF_UURF "convert to 32 bit fixed from extended dfp source with rounding mode" z196 zarch
+b942 clgdtr RRF_UURF "convert to 64 bit fixed logical from long dfp with rounding mode" z196 zarch
+b94a clgxtr RRF_UURF "convert to 64 bit fixed logical from extended dfp with rounding mode" z196 zarch
+b943 clfdtr RRF_UURF "convert to 32 bit fixed logical from long dfp with rounding mode" z196 zarch
+b94b clfxtr RRF_UURF "convert to 32 bit fixed logical from extended dfp with rounding mode" z196 zarch
+b3d1 ddtra RRF_FUFF2 "divide long dfp with rounding mode" z196 zarch
+b3d9 dxtra RRF_FUFF2 "divide extended dfp with rounding mode" z196 zarch
+b3d0 mdtra RRF_FUFF2 "multiply long dfp with rounding mode" z196 zarch
+b3d8 mxtra RRF_FUFF2 "multiply extended dfp with rounding mode" z196 zarch
+b3d3 sdtra RRF_FUFF2 "subtract long dfp with rounding mode" z196 zarch
+b3db sxtra RRF_FUFF2 "subtract extended dfp with rounding mode" z196 zarch
+b2b8 srnmb S_RD "set 3 bit bfp rounding mode" z196 zarch