From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Tue, 5 Mar 2019 19:28:25 +0000 (-0800)
Subject: Merge tag 'mips_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
X-Git-Tag: v5.15~6911
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d9862cfbe2099deb83f0e9c1932c91f2d9c50464;p=platform%2Fkernel%2Flinux-starfive.git

Merge tag 'mips_5.1' of git://git./linux/kernel/git/mips/linux

Pull MIPS updates from Paul Burton:

 - Support for the MIPSr6 MemoryMapID register & Global INValidate TLB
   (GINVT) instructions, allowing for more efficient TLB maintenance
   when running on a CPU such as the I6500 that supports these.

 - Enable huge page support for MIPS64r6.

 - Optimize post-DMA cache sync by removing that code entirely for
   kernel configurations in which we know it won't be needed.

 - The number of pages allocated for interrupt stacks is now calculated
   correctly, where before we would wastefully allocate too much memory
   in some configurations.

 - The ath79 platform migrates to devicetree.

 - The bcm47xx platform sees fixes for the Buffalo WHR-G54S board.

 - The ingenic/jz4740 platform gains support for appended devicetrees.

 - The cavium_octeon, lantiq, loongson32 & sgi-ip27 platforms all see
   cleanups as do various pieces of core architecture code.

* tag 'mips_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (66 commits)
  MIPS: lantiq: Remove separate GPHY Firmware loader
  MIPS: ingenic: Add support for appended devicetree
  MIPS: SGI-IP27: rework HUB interrupts
  MIPS: SGI-IP27: do boot CPU init later
  MIPS: SGI-IP27: do xtalk scanning later
  MIPS: SGI-IP27: use pr_info/pr_emerg and pr_cont to fix output
  MIPS: SGI-IP27: clean up bridge access and header files
  MIPS: SGI-IP27: get rid of volatile and hubreg_t
  MIPS: irq: Allocate accurate order pages for irq stack
  MIPS: dma-noncoherent: Remove bogus condition in dma_sync_phys()
  MIPS: eBPF: Remove REG_32BIT_ZERO_EX
  MIPS: eBPF: Always return sign extended 32b values
  MIPS: CM: Fix indentation
  MIPS: BCM47XX: Fix/improve Buffalo WHR-G54S support
  MIPS: OCTEON: program rx/tx-delay always from DT
  MIPS: OCTEON: delete board-specific link status
  MIPS: OCTEON: don't lie about interface type of CN3005 board
  MIPS: OCTEON: warn if deprecated link status is being used
  MIPS: OCTEON: add fixed-link nodes to in-kernel device tree
  MIPS: Delete unused flush_cache_sigtramp()
  ...
---

d9862cfbe2099deb83f0e9c1932c91f2d9c50464
diff --cc arch/mips/include/asm/barrier.h
index b7f6ac5,b48ee2c..b865e31
--- a/arch/mips/include/asm/barrier.h
+++ b/arch/mips/include/asm/barrier.h
@@@ -222,42 -236,11 +236,47 @@@
  #define __smp_mb__before_atomic()	__smp_mb__before_llsc()
  #define __smp_mb__after_atomic()	smp_llsc_mb()
  
 +/*
 + * Some Loongson 3 CPUs have a bug wherein execution of a memory access (load,
 + * store or pref) in between an ll & sc can cause the sc instruction to
 + * erroneously succeed, breaking atomicity. Whilst it's unusual to write code
 + * containing such sequences, this bug bites harder than we might otherwise
 + * expect due to reordering & speculation:
 + *
 + * 1) A memory access appearing prior to the ll in program order may actually
 + *    be executed after the ll - this is the reordering case.
 + *
 + *    In order to avoid this we need to place a memory barrier (ie. a sync
 + *    instruction) prior to every ll instruction, in between it & any earlier
 + *    memory access instructions. Many of these cases are already covered by
 + *    smp_mb__before_llsc() but for the remaining cases, typically ones in
 + *    which multiple CPUs may operate on a memory location but ordering is not
 + *    usually guaranteed, we use loongson_llsc_mb() below.
 + *
 + *    This reordering case is fixed by 3A R2 CPUs, ie. 3A2000 models and later.
 + *
 + * 2) If a conditional branch exists between an ll & sc with a target outside
 + *    of the ll-sc loop, for example an exit upon value mismatch in cmpxchg()
 + *    or similar, then misprediction of the branch may allow speculative
 + *    execution of memory accesses from outside of the ll-sc loop.
 + *
 + *    In order to avoid this we need a memory barrier (ie. a sync instruction)
 + *    at each affected branch target, for which we also use loongson_llsc_mb()
 + *    defined below.
 + *
 + *    This case affects all current Loongson 3 CPUs.
 + */
 +#ifdef CONFIG_CPU_LOONGSON3_WORKAROUNDS /* Loongson-3's LLSC workaround */
 +#define loongson_llsc_mb()	__asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
 +#else
 +#define loongson_llsc_mb()	do { } while (0)
 +#endif
 +
+ static inline void sync_ginv(void)
+ {
+ 	asm volatile("sync\t%0" :: "i"(STYPE_GINV));
+ }
+ 
  #include <asm-generic/barrier.h>
  
  #endif /* __ASM_BARRIER_H */