From: daeinki Date: Mon, 26 Oct 2009 06:31:00 +0000 (+0900) Subject: s5pc110: fb: updated lcd controller and lcd panel driver. X-Git-Tag: CES1223_2~173^2~1 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d96d4e27d9e4dd24deb541f068b7e3f42fb4075d;p=kernel%2Fu-boot.git s5pc110: fb: updated lcd controller and lcd panel driver. Signed-off-by: daeinki --- diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 447d910..60ba708 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -37,7 +37,7 @@ COBJS-$(CONFIG_SED156X) += sed156x.o COBJS-$(CONFIG_VIDEO_SM501) += sm501.o COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o -COBJS-$(CONFIG_S5PC1XXFB) += s5p-fb.o s5p-fimd.o tl2796.o +COBJS-$(CONFIG_S5PC1XXFB) += s5p-fb.o s5p-fimd.o s6e63m0.o #COBJS-$(CONFIG_S5PC1XXFB) += s5p-fb.o s5p_fimd_aquila.o tl2796_aquila.o #COBJS-$(CONFIG_S5PC1XXFB) += s5p-dualfb.o s5p-dualfimd.o tl2796_dual.o diff --git a/drivers/video/s5p-fimd.c b/drivers/video/s5p-fimd.c index 80cf5d0..c399b30 100644 --- a/drivers/video/s5p-fimd.c +++ b/drivers/video/s5p-fimd.c @@ -52,6 +52,7 @@ static unsigned long *lcd_base_addr; static vidinfo_t *pvid = NULL; extern unsigned long get_pll_clk(int pllreg); +extern void s5pc1xx_clock_init(void); void s5pc_fimd_lcd_init_mem(u_long screen_base, u_long fb_size, u_long palette_size) { @@ -64,91 +65,58 @@ void s5pc_fimd_lcd_init_mem(u_long screen_base, u_long fb_size, u_long palette_s void s5pc_c100_gpio_setup(void) { - /* set GPF0[0:7] for RGB Interface and Data lines */ - writel(0x22222222, S5PC100_GPIO_BASE(S5PC100_GPIO_F0_OFFSET)); - - /* set Data lines */ - writel(0x22222222, S5PC100_GPIO_BASE(S5PC100_GPIO_F1_OFFSET)); - writel(0x22222222, S5PC100_GPIO_BASE(S5PC100_GPIO_F2_OFFSET)); - writel(0x2222, S5PC100_GPIO_BASE(S5PC100_GPIO_F3_OFFSET)); - - /* set gpio configuration pin for MLCD_RST */ - writel(0x10000000, S5PC100_GPIO_BASE(S5PC100_GPIO_H1_OFFSET)); - - /* set gpio configuration pin for MLCD_ON */ - writel(0x1000, S5PC100_GPIO_BASE(S5PC100_GPIO_J1_OFFSET)); - writel(readl(S5PC100_GPIO_BASE(S5PC100_GPIO_J1_OFFSET+S5PC1XX_GPIO_DAT_OFFSET)) & 0xf7, - S5PC100_GPIO_BASE(S5PC100_GPIO_J1_OFFSET+S5PC1XX_GPIO_DAT_OFFSET)); - - /* set gpio configuration pin for DISPLAY_CS, DISPLAY_CLK and DISPLSY_SI */ - writel(0x11100000, S5PC100_GPIO_BASE(S5PC100_GPIO_K3_OFFSET)); } void s5pc_c110_gpio_setup(void) { - /* set GPF0[0:7] for RGB Interface and Data lines (32bit) */ - writel(0x22222222, S5PC110_GPIO_BASE(S5PC110_GPIO_F0_OFFSET)); - /* pull-up/down disable */ - writel(0x0, S5PC110_GPIO_BASE(S5PC110_GPIO_F0_OFFSET+S5PC1XX_GPIO_PULL_OFFSET)); - /* drive strength to max (24bit) */ - writel(0xffffff, S5PC110_GPIO_BASE(S5PC110_GPIO_F0_OFFSET+S5PC1XX_GPIO_DRV_OFFSET)); - - /* set Data lines (32bit) */ - writel(0x22222222, S5PC110_GPIO_BASE(S5PC110_GPIO_F1_OFFSET)); - writel(0x22222222, S5PC110_GPIO_BASE(S5PC110_GPIO_F2_OFFSET)); - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_F3_OFFSET)) & 0xFF0000, - S5PC110_GPIO_BASE(S5PC110_GPIO_F3_OFFSET)); - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_F3_OFFSET)) | 0x002222, - S5PC110_GPIO_BASE(S5PC110_GPIO_F3_OFFSET)); - - /* drive strength to max (24bit) */ - writel(0xffffff, S5PC110_GPIO_BASE(S5PC110_GPIO_F1_OFFSET+S5PC1XX_GPIO_DRV_OFFSET)); - writel(0xffffff, S5PC110_GPIO_BASE(S5PC110_GPIO_F2_OFFSET+S5PC1XX_GPIO_DRV_OFFSET)); - /* [11:0](drive stength level), [15:12](none), [21:16](Slew Rate) */ - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_F3_OFFSET+S5PC1XX_GPIO_DRV_OFFSET)) & 0x3FFF00, - S5PC110_GPIO_BASE(S5PC110_GPIO_F3_OFFSET+S5PC1XX_GPIO_DRV_OFFSET)); - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_F3_OFFSET+S5PC1XX_GPIO_DRV_OFFSET)) | 0x0000FF, - S5PC110_GPIO_BASE(S5PC110_GPIO_F3_OFFSET+S5PC1XX_GPIO_DRV_OFFSET)); - - /* pull-up/down disable */ - writel(0x0, S5PC110_GPIO_BASE(S5PC110_GPIO_F1_OFFSET+S5PC1XX_GPIO_PULL_OFFSET)); - writel(0x0, S5PC110_GPIO_BASE(S5PC110_GPIO_F2_OFFSET+S5PC1XX_GPIO_PULL_OFFSET)); - writel(0x0, S5PC110_GPIO_BASE(S5PC110_GPIO_F3_OFFSET+S5PC1XX_GPIO_PULL_OFFSET)); - + unsigned int i; + struct s5pc110_gpio *gpio = (struct s5pc110_gpio *) S5PC110_GPIO_BASE; + + for (i = 0; i < 8; i++) { + /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */ + gpio_cfg_pin(&gpio->gpio_f0, i, GPIO_FUNC(2)); + gpio_cfg_pin(&gpio->gpio_f1, i, GPIO_FUNC(2)); + gpio_cfg_pin(&gpio->gpio_f2, i, GPIO_FUNC(2)); + /* pull-up/down disable */ + gpio_set_pull(&gpio->gpio_f0, i, GPIO_PULL_NONE); + gpio_set_pull(&gpio->gpio_f1, i, GPIO_PULL_NONE); + gpio_set_pull(&gpio->gpio_f2, i, GPIO_PULL_NONE); + + /* drive strength to max (24bit) */ + gpio_set_drv(&gpio->gpio_f0, i, GPIO_DRV_4x); + gpio_set_rate(&gpio->gpio_f0, i, GPIO_DRV_SLOW); + gpio_set_drv(&gpio->gpio_f1, i, GPIO_DRV_4x); + gpio_set_rate(&gpio->gpio_f1, i, GPIO_DRV_SLOW); + gpio_set_drv(&gpio->gpio_f2, i, GPIO_DRV_4x); + gpio_set_rate(&gpio->gpio_f2, i, GPIO_DRV_SLOW); + } + + for (i =0; i < 4; i++) { + /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */ + gpio_cfg_pin(&gpio->gpio_f3, i, GPIO_PULL_UP); + /* pull-up/down disable */ + gpio_set_pull(&gpio->gpio_f3, i, GPIO_PULL_NONE); + /* drive strength to max (24bit) */ + gpio_set_drv(&gpio->gpio_f3, i, GPIO_DRV_4x); + gpio_set_rate(&gpio->gpio_f3, i, GPIO_DRV_SLOW); + } /* display output path selection (only [1:0] valid) */ writel(0x2, DCR); - /* set gpio configuration pin for MLCD_RST */ - /* for s5pc110 Universal board. - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_H1_OFFSET)) & 0x0fffffff, - S5PC110_GPIO_BASE(S5PC110_GPIO_H1_OFFSET)); - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_H1_OFFSET)) | 0x10000000, - S5PC110_GPIO_BASE(S5PC110_GPIO_H1_OFFSET)); - */ - - /* for s5pc110 Limo board. */ - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_5_OFFSET)) & 0xff0fffff, - S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_5_OFFSET)); - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_5_OFFSET)) | 0x00100000, - S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_5_OFFSET)); - - /* set gpio configuration pin for MLCD_ON and then to LOW */ - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_J1_OFFSET)) & 0xFFFF0FFF, - S5PC110_GPIO_BASE(S5PC110_GPIO_J1_OFFSET)); - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_J1_OFFSET)) | 0x00001000, - S5PC110_GPIO_BASE(S5PC110_GPIO_J1_OFFSET)); - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_J1_OFFSET+4)) & 0xf7, - S5PC110_GPIO_BASE(S5PC110_GPIO_J1_OFFSET+S5PC1XX_GPIO_DAT_OFFSET)); - - /* set gpio configuration pin for DISPLAY_CS, DISPLAY_CLK, DISPLSY_SI and LCD_ID */ - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_1_OFFSET)) & 0xFFFFFF0F, - S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_1_OFFSET)); - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_1_OFFSET)) | 0x00000010, - S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_1_OFFSET)); - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_4_OFFSET)) & 0xFFFF000F, - S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_4_OFFSET)); - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_4_OFFSET)) | 0x00001110, - S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_4_OFFSET)); + /* gpio pad configuration for LCD reset. */ + gpio_cfg_pin(&gpio->gpio_mp0_5, 5, GPIO_OUTPUT); + + /* gpio pad configuration for LCD ON. */ + gpio_cfg_pin(&gpio->gpio_j1, 3, GPIO_OUTPUT); + + /* gpio pad configuration for DISPLAY_CS, DISPLAY_CLK, DISPLAY_SO, DISPLAY_SI. */ + gpio_cfg_pin(&gpio->gpio_mp0_1, 1, GPIO_OUTPUT); + gpio_cfg_pin(&gpio->gpio_mp0_4, 1, GPIO_OUTPUT); + gpio_cfg_pin(&gpio->gpio_mp0_4, 2, GPIO_INPUT); + gpio_cfg_pin(&gpio->gpio_mp0_4, 3, GPIO_OUTPUT); + + s5pc1xx_clock_init(); + return; } @@ -224,7 +192,12 @@ static void s5pc_fimd_set_clock(void) pvid->vl_elw + pvid->vl_width) * (pvid->vl_vpw + pvid->vl_bfw + pvid->vl_efw + pvid->vl_height); - src_clock = get_pll_clk(MPLL); + if (get_pll_clk == NULL) { + printf("get_pll_clk is null.\n"); + return; + } + //src_clock = get_pll_clk(MPLL); + src_clock = 667000000; cfg = readl(ctrl_base + S5P_VIDCON0); cfg &= ~(S5P_VIDCON0_CLKSEL_MASK | S5P_VIDCON0_CLKVALUP_MASK | \ @@ -256,9 +229,9 @@ static void s5pc_fimd_set_clock(void) return; } -static s5pc_fimd_lcd_on(unsigned int win_id) +static void s5pc_fimd_lcd_on(unsigned int win_id) { - int cfg = 0; + unsigned int cfg = 0; /* display on */ cfg = readl(ctrl_base + S5P_VIDCON0); @@ -273,6 +246,20 @@ static s5pc_fimd_lcd_on(unsigned int win_id) udebug("wincon%d=%x\n", win_id, cfg); } +void s5pc_fimc_lcd_off(unsigned int win_id) +{ + unsigned int cfg = 0; + + cfg = readl(ctrl_base + S5P_VIDCON0); + cfg &= (S5P_VIDCON0_ENVID_DISABLE | S5P_VIDCON0_ENVID_F_DISABLE); + writel(cfg, ctrl_base + S5P_VIDCON0); + + cfg = readl(ctrl_base + S5P_WINCON(win_id)); + cfg &= S5P_WINCON_ENWIN_DISABLE; + writel(cfg, ctrl_base + S5P_WINCON(win_id)); +} + + void s5pc_fimd_lcd_init(vidinfo_t *vid) { unsigned int cfg = 0, rgb_mode, win_id = 0; diff --git a/drivers/video/s6e63m0.c b/drivers/video/s6e63m0.c index 79a9e99..b99c655 100644 --- a/drivers/video/s6e63m0.c +++ b/drivers/video/s6e63m0.c @@ -25,6 +25,8 @@ #include #include +struct s5pc110_gpio *gpio = (struct s5pc110_gpio *) S5PC110_GPIO_BASE; + #define SLEEPMSEC 0x1000 #define ENDDEF 0x2000 #define DEFMASK 0xFF00 @@ -33,24 +35,12 @@ #define PACKET_LEN 8 -#define S5PCFB_C110_CS_LOW writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_1_OFFSET+\ - S5PC1XX_GPIO_DAT_OFFSET)) & 0xfd, S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_1_OFFSET+\ - S5PC1XX_GPIO_DAT_OFFSET)) -#define S5PCFB_C110_CS_HIGH writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_1_OFFSET+\ - S5PC1XX_GPIO_DAT_OFFSET)) | 0x02, S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_1_OFFSET+\ - S5PC1XX_GPIO_DAT_OFFSET)) -#define S5PCFB_C110_CLK_LOW writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_4_OFFSET+\ - S5PC1XX_GPIO_DAT_OFFSET)) & 0xfd, S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_4_OFFSET+\ - S5PC1XX_GPIO_DAT_OFFSET)) -#define S5PCFB_C110_CLK_HIGH writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_4_OFFSET+\ - S5PC1XX_GPIO_DAT_OFFSET)) | 0x02, S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_4_OFFSET+\ - S5PC1XX_GPIO_DAT_OFFSET)) -#define S5PCFB_C110_SDA_LOW writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_4_OFFSET+\ - S5PC1XX_GPIO_DAT_OFFSET)) & 0xf7, S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_4_OFFSET+\ - S5PC1XX_GPIO_DAT_OFFSET)) -#define S5PCFB_C110_SDA_HIGH writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_4_OFFSET+\ - S5PC1XX_GPIO_DAT_OFFSET)) | 0x08, S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_4_OFFSET+\ - S5PC1XX_GPIO_DAT_OFFSET)) +#define S5PCFB_C110_CS_LOW gpio_set_value(&gpio->gpio_mp0_1, 1, 0) +#define S5PCFB_C110_CS_HIGH gpio_set_value(&gpio->gpio_mp0_1, 1, 1) +#define S5PCFB_C110_CLK_LOW gpio_set_value(&gpio->gpio_mp0_4, 1, 0) +#define S5PCFB_C110_CLK_HIGH gpio_set_value(&gpio->gpio_mp0_4, 1, 1) +#define S5PCFB_C110_SDA_LOW gpio_set_value(&gpio->gpio_mp0_4, 3, 0) +#define S5PCFB_C110_SDA_HIGH gpio_set_value(&gpio->gpio_mp0_4, 3, 1) const unsigned short SEQ_PANEL_CONDITION_SET[] = { 0xF8, 0x01, @@ -350,27 +340,15 @@ void lcd_panel_power_on(void) udelay(25000); /* set gpio data for MLCD_RST to HIGH */ - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_5_OFFSET+ - S5PC1XX_GPIO_DAT_OFFSET)) | 0x20, - S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_5_OFFSET+ - S5PC1XX_GPIO_DAT_OFFSET)); + gpio_set_value(&gpio->gpio_mp0_5, 5, 1); /* set gpio data for MLCD_ON to HIGH */ - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_J1_OFFSET+ - S5PC1XX_GPIO_DAT_OFFSET)) | 0x8, - S5PC110_GPIO_BASE(S5PC110_GPIO_J1_OFFSET+ - S5PC1XX_GPIO_DAT_OFFSET)); + gpio_set_value(&gpio->gpio_j1, 3, 1); /* set gpio data for MLCD_RST to LOW */ - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_5_OFFSET+ - S5PC1XX_GPIO_DAT_OFFSET)) & 0xdf, - S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_5_OFFSET+ - S5PC1XX_GPIO_DAT_OFFSET)); + gpio_set_value(&gpio->gpio_mp0_5, 5, 0); udelay(20); /* set gpio data for MLCD_RST to HIGH */ - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_5_OFFSET+ - S5PC1XX_GPIO_DAT_OFFSET)) | 0x20, - S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_5_OFFSET+ - S5PC1XX_GPIO_DAT_OFFSET)); + gpio_set_value(&gpio->gpio_mp0_5, 5, 1); udelay(120000); @@ -383,16 +361,14 @@ void lcd_panel_power_on(void) static inline void s6e63m0_c110_panel_hw_reset(void) { /* set gpio pin for MLCD_RST to LOW */ - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_H1_OFFSET+ - S5PC1XX_GPIO_DAT_OFFSET)) & 0x7f, - S5PC110_GPIO_BASE(S5PC110_GPIO_H1_OFFSET+ - S5PC1XX_GPIO_DAT_OFFSET)); - udelay(1); /* Shorter than 5 usec */ + gpio_set_value(&gpio->gpio_mp0_5, 5, 0); + + /* Shorter than 5 usec */ + udelay(1); + /* set gpio pin for MLCD_RST to HIGH */ - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_H1_OFFSET+ - S5PC1XX_GPIO_DAT_OFFSET)) | 0x80, - S5PC110_GPIO_BASE(S5PC110_GPIO_H1_OFFSET+ - S5PC1XX_GPIO_DAT_OFFSET)); + gpio_set_value(&gpio->gpio_mp0_5, 5, 1); + udelay(10000); } @@ -408,18 +384,9 @@ static void s6e63m0_panel_disable(void) void lcd_panel_init(void) { /* set gpio pin for DISPLAY_CS to HIGH */ - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_1_OFFSET+ - S5PC1XX_GPIO_DAT_OFFSET)) | 0x02, - S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_1_OFFSET+ - S5PC1XX_GPIO_DAT_OFFSET)); + gpio_set_value(&gpio->gpio_mp0_1, 1, 1); /* set gpio pin for DISPLAY_CLK to HIGH */ - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_4_OFFSET+ - S5PC1XX_GPIO_DAT_OFFSET)) | 0x02, - S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_4_OFFSET+ - S5PC1XX_GPIO_DAT_OFFSET)); + gpio_set_value(&gpio->gpio_mp0_4, 1, 1); /* set gpio pin for DISPLAY_SI to HIGH */ - writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_4_OFFSET+ - S5PC1XX_GPIO_DAT_OFFSET)) | 0x08, - S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_4_OFFSET+ - S5PC1XX_GPIO_DAT_OFFSET)); + gpio_set_value(&gpio->gpio_mp0_4, 3, 1); }