From: Andrzej Hajda <a.hajda@samsung.com>
Date: Thu, 10 Nov 2016 10:30:52 +0000 (+0100)
Subject: drm/bridge/sii8620: simplify MHL3 mode setting
X-Git-Tag: submit/tizen/20161216.052309~46
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d923c57d8752ad85ec8c5802c67ca022ae0a9b0f;p=platform%2Fkernel%2Flinux-exynos.git

drm/bridge/sii8620: simplify MHL3 mode setting

It is not necessary to set REG_COC_CTL0, REG_MHL_COC_CTL1 registers.

Change-Id: Id363df66baffe0be9f96e61597bc04a16bf42aad
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
---

diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c b/drivers/gpu/drm/bridge/sil-sii8620.c
index 1ef5924f75bf..92f5dd61129b 100644
--- a/drivers/gpu/drm/bridge/sil-sii8620.c
+++ b/drivers/gpu/drm/bridge/sil-sii8620.c
@@ -976,12 +976,8 @@ static void sii8620_set_mode(struct sii8620 *ctx, enum sii8620_mode mode)
 		);
 		break;
 	case CM_MHL3:
-		sii8620_write_seq_static(ctx,
-			REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE,
-			REG_COC_CTL0, 0x40,
-			REG_MHL_COC_CTL1, 0x07
-		);
-		break;
+		sii8620_write(ctx, REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE);
+		return;
 	case CM_DISCONNECTED:
 		break;
 	default: