From: Siarhei Siamashka Date: Sun, 13 Aug 2017 02:25:20 +0000 (+0300) Subject: arm: Exercise v7_arch_cp15_set_acr even without errata fixups X-Git-Tag: v2018.03-rc1~238 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d852600ef073205b1fa3e5b9539b15f2760ee164;p=platform%2Fkernel%2Fu-boot.git arm: Exercise v7_arch_cp15_set_acr even without errata fixups By applying this patch, we are ensuring that the code paths responsible for applying errata workarounds are also exercised on CPU revisions, which actually don't need these workarounds. Only CONFIG_ARM_ERRATA_621766, CONFIG_ARM_ERRATA_454179, CONFIG_ARM_ERRATA_725233 and CONFIG_ARM_ERRATA_430973 are covered by this patch (Cortex-A8). This improves code coverage when testing U-Boot builds on newer hardware. In particular, the problematic commit 00bbe96ebabb ("arm: omap: Unify get_device_type() function") would break both BeageBoard and BeagleBoard XM rather than just older BeagleBoard. As an additional bonus, we need fewer instructins and the SPL size is reduced. Signed-off-by: Siarhei Siamashka Reviewed-by: Tom Rini --- diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 95a0b52..7e26957 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -239,55 +239,47 @@ skip_errata_801819: #endif #ifdef CONFIG_ARM_ERRATA_454179 + mrc p15, 0, r0, c1, c0, 1 @ Read ACR + cmp r2, #0x21 @ Only on < r2p1 - bge skip_errata_454179 + orrlt r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits - mrc p15, 0, r0, c1, c0, 1 @ Read ACR - orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits push {r1-r5} @ Save the cpu info registers bl v7_arch_cp15_set_acr pop {r1-r5} @ Restore the cpu info - fall through - -skip_errata_454179: #endif #ifdef CONFIG_ARM_ERRATA_430973 + mrc p15, 0, r0, c1, c0, 1 @ Read ACR + cmp r2, #0x21 @ Only on < r2p1 - bge skip_errata_430973 + orrlt r0, r0, #(0x1 << 6) @ Set IBE bit - mrc p15, 0, r0, c1, c0, 1 @ Read ACR - orr r0, r0, #(0x1 << 6) @ Set IBE bit push {r1-r5} @ Save the cpu info registers bl v7_arch_cp15_set_acr pop {r1-r5} @ Restore the cpu info - fall through - -skip_errata_430973: #endif #ifdef CONFIG_ARM_ERRATA_621766 + mrc p15, 0, r0, c1, c0, 1 @ Read ACR + cmp r2, #0x21 @ Only on < r2p1 - bge skip_errata_621766 + orrlt r0, r0, #(0x1 << 5) @ Set L1NEON bit - mrc p15, 0, r0, c1, c0, 1 @ Read ACR - orr r0, r0, #(0x1 << 5) @ Set L1NEON bit push {r1-r5} @ Save the cpu info registers bl v7_arch_cp15_set_acr pop {r1-r5} @ Restore the cpu info - fall through - -skip_errata_621766: #endif #ifdef CONFIG_ARM_ERRATA_725233 + mrc p15, 1, r0, c9, c0, 2 @ Read L2ACR + cmp r2, #0x21 @ Only on < r2p1 (Cortex A8) - bge skip_errata_725233 + orrlt r0, r0, #(0x1 << 27) @ L2 PLD data forwarding disable - mrc p15, 1, r0, c9, c0, 2 @ Read L2ACR - orr r0, r0, #(0x1 << 27) @ L2 PLD data forwarding disable push {r1-r5} @ Save the cpu info registers bl v7_arch_cp15_set_l2aux_ctrl pop {r1-r5} @ Restore the cpu info - fall through - -skip_errata_725233: #endif #ifdef CONFIG_ARM_ERRATA_852421