From: Alex Deucher Date: Tue, 13 Feb 2018 19:37:36 +0000 (-0500) Subject: drm/amdgpu/powerplay/smu7: drop refresh rate checks for mclk switching X-Git-Tag: v4.19~1144^2~30^2~5 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d821792171a0457431dd57f0f2b8828c478b26ab;p=platform%2Fkernel%2Flinux-rpi.git drm/amdgpu/powerplay/smu7: drop refresh rate checks for mclk switching The logic has moved to cgs. mclk switching with DC at higher refresh rates should work. Reviewed-by: Eric Huang Signed-off-by: Alex Deucher Cc: Harry Wentland --- diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index 84600ff..0202841 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -2909,8 +2909,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, else disable_mclk_switching = ((1 < info.display_count) || disable_mclk_switching_for_frame_lock || - smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) || - (mode_info.refresh_rate > 120)); + smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us)); sclk = smu7_ps->performance_levels[0].engine_clock; mclk = smu7_ps->performance_levels[0].memory_clock;