From: Lionel Landwerlin Date: Mon, 31 Aug 2020 13:42:32 +0000 (+0300) Subject: intel/mi_builder: fix self modifying batches X-Git-Tag: upstream/21.2.3~9435 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d8154c40063d0d6114370c30c800676039e358ee;p=platform%2Fupstream%2Fmesa.git intel/mi_builder: fix self modifying batches So far we only write a maximum of 4 dwords further into the batch and it seems just going over the CS prefetch was enough. Turns out writing more dwords can delay the writes and we start prefetching stuff that hasn't landed in memory yet. This fixes the issue by stalling the CS to ensure the writes have landed before we go over the prefetch. Signed-off-by: Lionel Landwerlin Fixes: 796fccce631bf8 ("intel/mi-builder: add framework for self modifying batches") Reviewed-by: Marcin Ślusarz Part-of: --- diff --git a/src/intel/common/gen_mi_builder.h b/src/intel/common/gen_mi_builder.h index 4802b70..5b80170 100644 --- a/src/intel/common/gen_mi_builder.h +++ b/src/intel/common/gen_mi_builder.h @@ -967,6 +967,13 @@ gen_mi_store_address(struct gen_mi_builder *b, static inline void gen_mi_self_mod_barrier(struct gen_mi_builder *b) { + /* First make sure all the memory writes from previous modifying commands + * have landed. We want to do this before going through the CS cache, + * otherwise we could be fetching memory that hasn't been written to yet. + */ + gen_mi_builder_emit(b, GENX(PIPE_CONTROL), pc) { + pc.CommandStreamerStallEnable = true; + } /* Documentation says Gen11+ should be able to invalidate the command cache * but experiment show it doesn't work properly, so for now just get over * the CS prefetch.