From: Tomi Valkeinen Date: Fri, 25 Apr 2014 08:46:16 +0000 (+0300) Subject: OMAPDSS: Fix writes to DISPC_POL_FREQ X-Git-Tag: v4.9.8~6270^2~23^2~15 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d80e02ef343379cfcef211ab4f042fc4a5b26100;p=platform%2Fkernel%2Flinux-rpi3.git OMAPDSS: Fix writes to DISPC_POL_FREQ When omapdss writes to DISPC_POL_FREQ register, it always ORs the bits with the current contents of the register, never clearing the old ones, causing wrong signal polarity settings. As we write all the bits in DISPC_POL_FREQ, we don't need to care about the current contents of the register. So fix the issue by constructing new register value from scratch. Signed-off-by: Tomi Valkeinen --- diff --git a/drivers/video/fbdev/omap2/dss/dispc.c b/drivers/video/fbdev/omap2/dss/dispc.c index 07db792..7aa33b0 100644 --- a/drivers/video/fbdev/omap2/dss/dispc.c +++ b/drivers/video/fbdev/omap2/dss/dispc.c @@ -2945,13 +2945,13 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw, BUG(); } - l = dispc_read_reg(DISPC_POL_FREQ(channel)); - l |= FLD_VAL(onoff, 17, 17); - l |= FLD_VAL(rf, 16, 16); - l |= FLD_VAL(de_level, 15, 15); - l |= FLD_VAL(ipc, 14, 14); - l |= FLD_VAL(hsync_level, 13, 13); - l |= FLD_VAL(vsync_level, 12, 12); + l = FLD_VAL(onoff, 17, 17) | + FLD_VAL(rf, 16, 16) | + FLD_VAL(de_level, 15, 15) | + FLD_VAL(ipc, 14, 14) | + FLD_VAL(hsync_level, 13, 13) | + FLD_VAL(vsync_level, 12, 12); + dispc_write_reg(DISPC_POL_FREQ(channel), l); }