From: Zhigang Gong <zhigang.gong@intel.com>
Date: Fri, 16 May 2014 07:57:24 +0000 (+0800)
Subject: GBE: refine disassembly code to show null register's type.
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d7a940d5f2fab8be42bba6f1affd97df3c5d6e69;p=contrib%2Fbeignet.git

GBE: refine disassembly code to show null register's type.

We should show null register's type in the assembly output, as
if a null reigster is using a wrong type, such as the following
instruction:

cmp.le(8)      null:UW         g2<8,8,1>:F    0.1F

It is a fatal error from the hardware point of view. We should
output that information.

Signed-off-by: Zhigang Gong <zhigang.gong@intel.com>
Reviewed-by: "Song, Ruiling" <ruiling.song@intel.com>
---

diff --git a/backend/src/backend/gen/gen_mesa_disasm.c b/backend/src/backend/gen/gen_mesa_disasm.c
index 871277b..81c33a6 100644
--- a/backend/src/backend/gen/gen_mesa_disasm.c
+++ b/backend/src/backend/gen/gen_mesa_disasm.c
@@ -254,14 +254,14 @@ static const char *access_mode[2] = {
 };
 
 static const char *reg_encoding[8] = {
-  [0] = "UD",
-  [1] = "D",
-  [2] = "UW",
-  [3] = "W",
-  [4] = "UB",
-  [5] = "B",
-  [6] = "DF",
-  [7] = "F"
+  [0] = ":UD",
+  [1] = ":D",
+  [2] = ":UW",
+  [3] = ":W",
+  [4] = ":UB",
+  [5] = ":B",
+  [6] = ":DF",
+  [7] = ":F"
 };
 
 int reg_type_size[8] = {
@@ -542,8 +542,10 @@ static int dest (FILE *file, const union GenNativeInstruction *inst)
     if (inst->bits1.da1.dest_address_mode == GEN_ADDRESS_DIRECT)
     {
       err |= reg (file, inst->bits1.da1.dest_reg_file, inst->bits1.da1.dest_reg_nr);
-      if (err == -1)
+      if (err == -1) {
+        control (file, "dest reg encoding", reg_encoding, inst->bits1.da1.dest_reg_type, NULL);
         return 0;
+      }
       if (inst->bits1.da1.dest_subreg_nr)
         format (file, ".%d", inst->bits1.da1.dest_subreg_nr /
             reg_type_size[inst->bits1.da1.dest_reg_type]);