From: Ashutosh Dixit Date: Thu, 8 Sep 2022 15:58:21 +0000 (-0700) Subject: drm/i915/gt: Fix perf limit reasons bit positions X-Git-Tag: v6.1-rc5~437^2^2~1 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d654f60898d56ffda461ef4ffd7bbe15159feb8d;p=platform%2Fkernel%2Flinux-starfive.git drm/i915/gt: Fix perf limit reasons bit positions Perf limit reasons bit positions were off by one. Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency interfaces") Cc: stable@vger.kernel.org # v5.18+ Signed-off-by: Ashutosh Dixit Acked-by: Andi Shyti Reviewed-by: Sujaritha Sundaresan Signed-off-by: Matt Roper Link: https://patchwork.freedesktop.org/patch/msgid/20220908155821.1662110-1-ashutosh.dixit@intel.com Signed-off-by: Joonas Lahtinen (cherry picked from commit 60017f34fc334d1bb25476b0b0996b4073e76c90) Signed-off-by: Rodrigo Vivi --- diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3168d70..135d04c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1857,14 +1857,14 @@ #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8) #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 -#define PROCHOT_MASK REG_BIT(1) -#define THERMAL_LIMIT_MASK REG_BIT(2) -#define RATL_MASK REG_BIT(6) -#define VR_THERMALERT_MASK REG_BIT(7) -#define VR_TDC_MASK REG_BIT(8) -#define POWER_LIMIT_4_MASK REG_BIT(9) -#define POWER_LIMIT_1_MASK REG_BIT(11) -#define POWER_LIMIT_2_MASK REG_BIT(12) +#define PROCHOT_MASK REG_BIT(0) +#define THERMAL_LIMIT_MASK REG_BIT(1) +#define RATL_MASK REG_BIT(5) +#define VR_THERMALERT_MASK REG_BIT(6) +#define VR_TDC_MASK REG_BIT(7) +#define POWER_LIMIT_4_MASK REG_BIT(8) +#define POWER_LIMIT_1_MASK REG_BIT(10) +#define POWER_LIMIT_2_MASK REG_BIT(11) #define CHV_CLK_CTL1 _MMIO(0x101100) #define VLV_CLK_CTL2 _MMIO(0x101104)